drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/mmsch_v5_0.h- Extension
.h- Size
- 4381 bytes
- Lines
- 145
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu_vcn.h
Detected Declarations
struct mmsch_v5_0_table_infostruct mmsch_v5_0_init_headerstruct mmsch_v5_0_cmd_direct_reg_headerstruct mmsch_v5_0_cmd_indirect_reg_headerstruct mmsch_v5_0_cmd_direct_writestruct mmsch_v5_0_cmd_direct_read_modify_writestruct mmsch_v5_0_cmd_direct_pollingstruct mmsch_v5_0_cmd_endstruct mmsch_v5_0_cmd_indirect_writeenum mmsch_v5_0_command_type
Annotated Snippet
struct mmsch_v5_0_table_info {
uint32_t init_status;
uint32_t table_offset;
uint32_t table_size;
};
struct mmsch_v5_0_init_header {
uint32_t version;
uint32_t total_size;
struct mmsch_v5_0_table_info vcn0;
struct mmsch_v5_0_table_info mjpegdec0[5];
struct mmsch_v5_0_table_info mjpegdec1[5];
};
struct mmsch_v5_0_cmd_direct_reg_header {
uint32_t reg_offset : 28;
uint32_t command_type : 4;
};
struct mmsch_v5_0_cmd_indirect_reg_header {
uint32_t reg_offset : 20;
uint32_t reg_idx_space : 8;
uint32_t command_type : 4;
};
struct mmsch_v5_0_cmd_direct_write {
struct mmsch_v5_0_cmd_direct_reg_header cmd_header;
uint32_t reg_value;
};
struct mmsch_v5_0_cmd_direct_read_modify_write {
struct mmsch_v5_0_cmd_direct_reg_header cmd_header;
uint32_t write_data;
uint32_t mask_value;
};
struct mmsch_v5_0_cmd_direct_polling {
struct mmsch_v5_0_cmd_direct_reg_header cmd_header;
uint32_t mask_value;
uint32_t wait_value;
};
struct mmsch_v5_0_cmd_end {
struct mmsch_v5_0_cmd_direct_reg_header cmd_header;
};
struct mmsch_v5_0_cmd_indirect_write {
struct mmsch_v5_0_cmd_indirect_reg_header cmd_header;
uint32_t reg_value;
};
#define MMSCH_V5_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
size = sizeof(struct mmsch_v5_0_cmd_direct_read_modify_write); \
size_dw = size / 4; \
direct_rd_mod_wt.cmd_header.reg_offset = reg; \
direct_rd_mod_wt.mask_value = mask; \
direct_rd_mod_wt.write_data = data; \
memcpy((void *)table_loc, &direct_rd_mod_wt, size); \
table_loc += size_dw; \
table_size += size_dw; \
}
#define MMSCH_V5_0_INSERT_DIRECT_WT(reg, value) { \
size = sizeof(struct mmsch_v5_0_cmd_direct_write); \
size_dw = size / 4; \
direct_wt.cmd_header.reg_offset = reg; \
direct_wt.reg_value = value; \
memcpy((void *)table_loc, &direct_wt, size); \
table_loc += size_dw; \
table_size += size_dw; \
}
#define MMSCH_V5_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
size = sizeof(struct mmsch_v5_0_cmd_direct_polling); \
size_dw = size / 4; \
direct_poll.cmd_header.reg_offset = reg; \
direct_poll.mask_value = mask; \
direct_poll.wait_value = wait; \
memcpy((void *)table_loc, &direct_poll, size); \
table_loc += size_dw; \
table_size += size_dw; \
}
#define MMSCH_V5_0_INSERT_END() { \
size = sizeof(struct mmsch_v5_0_cmd_end); \
size_dw = size / 4; \
memcpy((void *)table_loc, &end, size); \
table_loc += size_dw; \
table_size += size_dw; \
}
Annotation
- Immediate include surface: `amdgpu_vcn.h`.
- Detected declarations: `struct mmsch_v5_0_table_info`, `struct mmsch_v5_0_init_header`, `struct mmsch_v5_0_cmd_direct_reg_header`, `struct mmsch_v5_0_cmd_indirect_reg_header`, `struct mmsch_v5_0_cmd_direct_write`, `struct mmsch_v5_0_cmd_direct_read_modify_write`, `struct mmsch_v5_0_cmd_direct_polling`, `struct mmsch_v5_0_cmd_end`, `struct mmsch_v5_0_cmd_indirect_write`, `enum mmsch_v5_0_command_type`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.