drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c- Extension
.c- Size
- 13309 bytes
- Lines
- 370
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
nbio/nbio_6_3_2_offset.hnbio/nbio_6_3_2_sh_mask.hamdgpu.hnbio_v6_3_2.h
Detected Declarations
function filesfunction nbio_v6_3_2_get_pcie_data_offsetfunction nbio_v6_3_2_get_pcie_index_hi_offsetfunction nbio_v6_3_2_get_rev_idfunction nbio_v6_3_2_mc_access_enablefunction nbio_v6_3_2_init_registersfunction nbio_v6_3_2_get_memsizefunction nbio_v6_3_2_enable_doorbell_aperturefunction nbio_v6_3_2_enable_doorbell_selfring_aperturefunction nbio_v6_3_2_enable_doorbell_interruptfunction nbio_v6_3_2_ih_controlfunction nbio_v6_3_2_ih_doorbell_rangefunction nbio_v6_3_2_gc_doorbell_initfunction nbio_v6_3_2_sdma_doorbell_rangefunction nbio_v6_3_2_vcn_doorbell_rangefunction nbio_v6_3_2_get_compute_partition_modefunction nbio_v6_3_2_is_nps_switch_requestedfunction nbio_v6_3_2_get_memory_partition_mode
Annotated Snippet
if (use_doorbell) {
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
S2A_DOORBELL_PORT6_ENABLE,
0x1);
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
S2A_DOORBELL_PORT6_AWID,
0xe);
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
S2A_DOORBELL_PORT6_RANGE_OFFSET,
doorbell_index);
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
S2A_DOORBELL_PORT6_RANGE_SIZE,
doorbell_size);
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE,
0xe);
doorbell_range1 = REG_SET_FIELD(doorbell_range1,
GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1,
S2A_DOORBELL_PORT6_TARGET_PORT_TYPE,
0x3);
doorbell_range1 = REG_SET_FIELD(doorbell_range1,
GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1,
S2A_DOORBELL_PORT6_TARGET_DIEID,
0x0);
doorbell_range1 = REG_SET_FIELD(doorbell_range1,
GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1,
S2A_DOORBELL_PORT6_TARGET_PORT_ID,
0x0);
}
WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, doorbell_range);
WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1, doorbell_range1);
}
}
static void nbio_v6_3_2_vcn_doorbell_range(struct amdgpu_device *adev,
bool use_doorbell, int doorbell_index,
int instance)
{
u32 doorbell_range = 0;
u32 doorbell_range1 = 0;
if (use_doorbell) {
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
S2A_DOORBELL_PORT2_ENABLE,
0x1);
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
S2A_DOORBELL_PORT2_AWID,
(instance % adev->vcn.num_inst_per_aid) ? 0x7 : 0x4);
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
S2A_DOORBELL_PORT2_RANGE_OFFSET,
doorbell_index);
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
S2A_DOORBELL_PORT2_RANGE_SIZE,
8);
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE,
(instance % adev->vcn.num_inst_per_aid) ? 0x7 : 0x4);
doorbell_range1 = REG_SET_FIELD(doorbell_range1,
GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1,
S2A_DOORBELL_PORT2_TARGET_PORT_TYPE,
0x3);
doorbell_range1 = REG_SET_FIELD(doorbell_range1,
GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1,
S2A_DOORBELL_PORT2_TARGET_DIEID,
(instance / adev->vcn.num_inst_per_aid) ? 0x3 : 0x0);
doorbell_range1 = REG_SET_FIELD(doorbell_range1,
GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1,
S2A_DOORBELL_PORT2_TARGET_PORT_ID,
0x0);
}
switch (instance) {
case 0:
WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range);
WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1, doorbell_range1);
break;
case 1:
WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, doorbell_range);
WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1, doorbell_range1);
Annotation
- Immediate include surface: `nbio/nbio_6_3_2_offset.h`, `nbio/nbio_6_3_2_sh_mask.h`, `amdgpu.h`, `nbio_v6_3_2.h`.
- Detected declarations: `function files`, `function nbio_v6_3_2_get_pcie_data_offset`, `function nbio_v6_3_2_get_pcie_index_hi_offset`, `function nbio_v6_3_2_get_rev_id`, `function nbio_v6_3_2_mc_access_enable`, `function nbio_v6_3_2_init_registers`, `function nbio_v6_3_2_get_memsize`, `function nbio_v6_3_2_enable_doorbell_aperture`, `function nbio_v6_3_2_enable_doorbell_selfring_aperture`, `function nbio_v6_3_2_enable_doorbell_interrupt`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.