drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c
Extension
.c
Size
23519 bytes
Lines
697
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

for_each_inst(i, adev->aid_mask) {
			baco_cntl = RREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL);
			if (baco_cntl & (BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK |
					 BIF_BX0_BACO_CNTL__BACO_EN_MASK)) {
				baco_cntl &= ~(
					BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK |
					BIF_BX0_BACO_CNTL__BACO_EN_MASK);
				dev_dbg(adev->dev,
					"Unsetting baco dummy mode %x",
					baco_cntl);
				WREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL,
					     baco_cntl);
			}
		}
	}
}

#define MMIO_REG_HOLE_OFFSET 0x1A000

static void nbio_v7_9_set_reg_remap(struct amdgpu_device *adev)
{
	if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
		adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
		adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
	} else {
		adev->rmmio_remap.reg_offset =
			SOC15_REG_OFFSET(
				NBIO, 0,
				regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
			<< 2;
		adev->rmmio_remap.bus_addr = 0;
	}
}

const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
	.get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
	.get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
	.get_pcie_index_offset = nbio_v7_9_get_pcie_index_offset,
	.get_pcie_data_offset = nbio_v7_9_get_pcie_data_offset,
	.get_pcie_index_hi_offset = nbio_v7_9_get_pcie_index_hi_offset,
	.get_rev_id = nbio_v7_9_get_rev_id,
	.mc_access_enable = nbio_v7_9_mc_access_enable,
	.get_memsize = nbio_v7_9_get_memsize,
	.sdma_doorbell_range = nbio_v7_9_sdma_doorbell_range,
	.vcn_doorbell_range = nbio_v7_9_vcn_doorbell_range,
	.enable_doorbell_aperture = nbio_v7_9_enable_doorbell_aperture,
	.enable_doorbell_selfring_aperture = nbio_v7_9_enable_doorbell_selfring_aperture,
	.ih_doorbell_range = nbio_v7_9_ih_doorbell_range,
	.enable_doorbell_interrupt = nbio_v7_9_enable_doorbell_interrupt,
	.update_medium_grain_clock_gating = nbio_v7_9_update_medium_grain_clock_gating,
	.update_medium_grain_light_sleep = nbio_v7_9_update_medium_grain_light_sleep,
	.get_clockgating_state = nbio_v7_9_get_clockgating_state,
	.ih_control = nbio_v7_9_ih_control,
	.remap_hdp_registers = nbio_v7_9_remap_hdp_registers,
	.get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
	.get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
	.is_nps_switch_requested = nbio_v7_9_is_nps_switch_requested,
	.init_registers = nbio_v7_9_init_registers,
	.set_reg_remap = nbio_v7_9_set_reg_remap,
};

static void nbio_v7_9_query_ras_error_count(struct amdgpu_device *adev,
					void *ras_error_status)
{
}

static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
{
	uint32_t bif_doorbell_intr_cntl;
	struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
	struct ras_err_data err_data;
	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);

	if (amdgpu_ras_error_data_init(&err_data))
		return;

	bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);

	if (REG_GET_FIELD(bif_doorbell_intr_cntl,
		BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
		/* driver has to clear the interrupt status when bif ring is disabled */
		bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
						BIF_BX0_BIF_DOORBELL_INT_CNTL,
						RAS_CNTLR_INTERRUPT_CLEAR, 1);
		WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);

		if (!ras->disable_ras_err_cnt_harvest) {
			/*
			 * clear error status after ras_controller_intr
			 * according to hw team and count ue number

Annotation

Implementation Notes