drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c- Extension
.c- Size
- 90196 bytes
- Lines
- 2742
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hlinux/firmware.hlinux/module.hlinux/pci.hamdgpu.hamdgpu_ucode.hamdgpu_trace.hsdma0/sdma0_4_2_offset.hsdma0/sdma0_4_2_sh_mask.hsdma1/sdma1_4_2_offset.hsdma1/sdma1_4_2_sh_mask.hsdma2/sdma2_4_2_2_offset.hsdma2/sdma2_4_2_2_sh_mask.hsdma3/sdma3_4_2_2_offset.hsdma3/sdma3_4_2_2_sh_mask.hsdma4/sdma4_4_2_2_offset.hsdma4/sdma4_4_2_2_sh_mask.hsdma5/sdma5_4_2_2_offset.hsdma5/sdma5_4_2_2_sh_mask.hsdma6/sdma6_4_2_2_offset.hsdma6/sdma6_4_2_2_sh_mask.hsdma7/sdma7_4_2_2_offset.hsdma7/sdma7_4_2_2_sh_mask.hsdma0/sdma0_4_1_default.hsoc15_common.hsoc15.hvega10_sdma_pkt_open.hivsrcid/sdma0/irqsrcs_sdma0_4_0.hivsrcid/sdma1/irqsrcs_sdma1_4_0.hamdgpu_ras.hsdma_v4_4.h
Detected Declarations
function sdma_v4_0_get_reg_offsetfunction sdma_v4_0_seq_to_irq_idfunction sdma_v4_0_irq_id_to_seqfunction sdma_v4_0_init_golden_registersfunction sdma_v4_0_setup_ulvfunction driverfunction hardwarefunction hardwarefunction hardwarefunction hardwarefunction hardwarefunction sdma_v4_0_ring_insert_nopfunction ringfunction sdma_v4_0_wait_reg_memfunction sdma_v4_0_ring_emit_hdp_flushfunction neededfunction buffersfunction queuesfunction enginesfunction sdma_v4_0_rb_cntlfunction themfunction themfunction sdma_v4_1_update_power_gatingfunction sdma_v4_1_init_power_gatingfunction sdma_v4_0_init_pgfunction themfunction sdma_v4_0_load_microcodefunction themfunction sdma_v4_0_ring_test_ringfunction ringfunction sDMAfunction sDMAfunction sDMAfunction sdma_v4_0_ring_pad_ibfunction completedfunction sDMAfunction sdma_v4_0_ring_emit_wregfunction sdma_v4_0_ring_emit_reg_waitfunction sdma_v4_0_fw_support_paging_queuefunction sdma_v4_0_early_initfunction sdma_v4_0_late_initfunction sdma_v4_0_sw_initfunction sdma_v4_0_sw_finifunction sdma_v4_0_hw_initfunction sdma_v4_0_hw_finifunction sdma_v4_0_suspendfunction sdma_v4_0_resumefunction sdma_v4_0_is_idle
Annotated Snippet
IP_VERSION(4, 4, 0)) {
/* Acturus & Aldebaran will leverage the same FW memory
for every SDMA instance */
ret = amdgpu_sdma_init_microcode(adev, 0, true);
break;
} else {
ret = amdgpu_sdma_init_microcode(adev, i, false);
if (ret)
return ret;
}
}
return ret;
}
/**
* sdma_v4_0_ring_get_rptr - get the current read pointer
*
* @ring: amdgpu ring pointer
*
* Get the current rptr from the hardware (VEGA10+).
*/
static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring)
{
u64 *rptr;
/* XXX check if swapping is necessary on BE */
rptr = ((u64 *)ring->rptr_cpu_addr);
DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
return ((*rptr) >> 2);
}
/**
* sdma_v4_0_ring_get_wptr - get the current write pointer
*
* @ring: amdgpu ring pointer
*
* Get the current wptr from the hardware (VEGA10+).
*/
static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
u64 wptr;
if (ring->use_doorbell) {
/* XXX check if swapping is necessary on BE */
wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
} else {
wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI);
wptr = wptr << 32;
wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR);
DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
ring->me, wptr);
}
return wptr >> 2;
}
/**
* sdma_v4_0_ring_set_wptr - commit the write pointer
*
* @ring: amdgpu ring pointer
*
* Write the wptr back to the hardware (VEGA10+).
*/
static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
DRM_DEBUG("Setting write pointer\n");
if (ring->use_doorbell) {
u64 *wb = (u64 *)ring->wptr_cpu_addr;
DRM_DEBUG("Using doorbell -- "
"wptr_offs == 0x%08x "
"lower_32_bits(ring->wptr << 2) == 0x%08x "
"upper_32_bits(ring->wptr << 2) == 0x%08x\n",
ring->wptr_offs,
lower_32_bits(ring->wptr << 2),
upper_32_bits(ring->wptr << 2));
/* XXX check if swapping is necessary on BE */
WRITE_ONCE(*wb, (ring->wptr << 2));
DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
ring->doorbell_index, ring->wptr << 2);
WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
} else {
DRM_DEBUG("Not using doorbell -- "
"mmSDMA%i_GFX_RB_WPTR == 0x%08x "
Annotation
- Immediate include surface: `linux/delay.h`, `linux/firmware.h`, `linux/module.h`, `linux/pci.h`, `amdgpu.h`, `amdgpu_ucode.h`, `amdgpu_trace.h`, `sdma0/sdma0_4_2_offset.h`.
- Detected declarations: `function sdma_v4_0_get_reg_offset`, `function sdma_v4_0_seq_to_irq_id`, `function sdma_v4_0_irq_id_to_seq`, `function sdma_v4_0_init_golden_registers`, `function sdma_v4_0_setup_ulv`, `function driver`, `function hardware`, `function hardware`, `function hardware`, `function hardware`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.