drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c- Extension
.c- Size
- 78313 bytes
- Lines
- 2595
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hlinux/firmware.hlinux/module.hlinux/pci.hamdgpu.hamdgpu_xcp.hamdgpu_ucode.hamdgpu_trace.hamdgpu_reset.hsdma/sdma_4_4_2_offset.hsdma/sdma_4_4_2_sh_mask.hsoc15_common.hsoc15.hvega10_sdma_pkt_open.hivsrcid/sdma0/irqsrcs_sdma0_4_0.hivsrcid/sdma1/irqsrcs_sdma1_4_0.hamdgpu_ras.h
Detected Declarations
function sdma_v4_4_2_get_reg_offsetfunction sdma_v4_4_2_seq_to_irq_idfunction sdma_v4_4_2_irq_id_to_seqfunction sdma_v4_4_2_inst_init_golden_registersfunction driverfunction sdma_v4_4_2_ring_get_rptrfunction sdma_v4_4_2_ring_get_wptrfunction sdma_v4_4_2_ring_set_wptrfunction sdma_v4_4_2_page_ring_get_wptrfunction sdma_v4_4_2_page_ring_set_wptrfunction sdma_v4_4_2_ring_insert_nopfunction sdma_v4_4_2_ring_emit_ibfunction sdma_v4_4_2_wait_reg_memfunction sdma_v4_4_2_ring_emit_hdp_flushfunction sdma_v4_4_2_ring_emit_fencefunction sdma_v4_4_2_inst_gfx_stopfunction for_each_instfunction sdma_v4_4_2_inst_rlc_stopfunction for_each_instfunction sdma_v4_4_2_inst_ctx_switch_enablefunction for_each_instfunction sdma_v4_4_2_inst_enablefunction for_each_instfunction sdma_v4_4_2_rb_cntlfunction sdma_v4_4_2_gfx_resumefunction sdma_v4_4_2_page_resumefunction sdma_v4_4_2_init_pgfunction sdma_v4_4_2_inst_load_microcodefunction for_each_instfunction sdma_v4_4_2_inst_startfunction sdma_v4_4_2_ring_test_ringfunction sdma_v4_4_2_ring_test_ibfunction sdma_v4_4_2_vm_copy_ptefunction sdma_v4_4_2_vm_write_ptefunction sdma_v4_4_2_vm_set_pte_pdefunction sdma_v4_4_2_ring_pad_ibfunction completedfunction sdma_v4_4_2_ring_emit_vm_flushfunction sdma_v4_4_2_ring_emit_wregfunction sdma_v4_4_2_ring_emit_reg_waitfunction sdma_v4_4_2_fw_support_paging_queuefunction sdma_v4_4_2_early_initfunction sdma_v4_4_2_late_initfunction sdma_v4_4_2_sw_initfunction sdma_v4_4_2_sw_finifunction sdma_v4_4_2_hw_initfunction sdma_v4_4_2_hw_finifunction sdma_v4_4_2_suspend
Annotated Snippet
amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) {
ret = amdgpu_sdma_init_microcode(adev, 0, true);
break;
} else {
ret = amdgpu_sdma_init_microcode(adev, i, false);
if (ret)
return ret;
}
}
return ret;
}
/**
* sdma_v4_4_2_ring_get_rptr - get the current read pointer
*
* @ring: amdgpu ring pointer
*
* Get the current rptr from the hardware.
*/
static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring)
{
u64 rptr;
/* XXX check if swapping is necessary on BE */
rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs]));
DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr);
return rptr >> 2;
}
/**
* sdma_v4_4_2_ring_get_wptr - get the current write pointer
*
* @ring: amdgpu ring pointer
*
* Get the current wptr from the hardware.
*/
static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
u64 wptr;
if (ring->use_doorbell) {
/* XXX check if swapping is necessary on BE */
wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
} else {
wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
wptr = wptr << 32;
wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
ring->me, wptr);
}
return wptr >> 2;
}
/**
* sdma_v4_4_2_ring_set_wptr - commit the write pointer
*
* @ring: amdgpu ring pointer
*
* Write the wptr back to the hardware.
*/
static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
DRM_DEBUG("Setting write pointer\n");
if (ring->use_doorbell) {
u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
DRM_DEBUG("Using doorbell -- "
"wptr_offs == 0x%08x "
"lower_32_bits(ring->wptr) << 2 == 0x%08x "
"upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
ring->wptr_offs,
lower_32_bits(ring->wptr << 2),
upper_32_bits(ring->wptr << 2));
/* XXX check if swapping is necessary on BE */
WRITE_ONCE(*wb, (ring->wptr << 2));
DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
ring->doorbell_index, ring->wptr << 2);
WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
} else {
DRM_DEBUG("Not using doorbell -- "
"regSDMA%i_GFX_RB_WPTR == 0x%08x "
"regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
ring->me,
Annotation
- Immediate include surface: `linux/delay.h`, `linux/firmware.h`, `linux/module.h`, `linux/pci.h`, `amdgpu.h`, `amdgpu_xcp.h`, `amdgpu_ucode.h`, `amdgpu_trace.h`.
- Detected declarations: `function sdma_v4_4_2_get_reg_offset`, `function sdma_v4_4_2_seq_to_irq_id`, `function sdma_v4_4_2_irq_id_to_seq`, `function sdma_v4_4_2_inst_init_golden_registers`, `function driver`, `function sdma_v4_4_2_ring_get_rptr`, `function sdma_v4_4_2_ring_get_wptr`, `function sdma_v4_4_2_ring_set_wptr`, `function sdma_v4_4_2_page_ring_get_wptr`, `function sdma_v4_4_2_page_ring_set_wptr`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.