drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/sdma_v4_4.c
Extension
.c
Size
9214 bytes
Lines
275
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (sec_cnt) {
			dev_info(adev->dev, "Detected %s in SDMA%d, SED %d\n",
				 sdma_v4_4_ras_fields[i].name,
				 instance, sec_cnt);
			*sec_count += sec_cnt;
		}
	}
}

static int sdma_v4_4_query_ras_error_count_by_instance(struct amdgpu_device *adev,
					   uint32_t instance,
					   void *ras_error_status)
{
	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
	uint32_t sec_count = 0;
	uint32_t reg_value = 0;
	uint32_t reg_offset = 0;

	reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER);
	reg_value = RREG32(reg_offset);
	/* double bit error is not supported */
	if (reg_value)
		sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER, reg_value,
					      instance, &sec_count);

	reg_offset = sdma_v4_4_get_reg_offset(adev, instance, regSDMA0_EDC_COUNTER2);
	reg_value = RREG32(reg_offset);
	/* double bit error is not supported */
	if (reg_value)
		sdma_v4_4_get_ras_error_count(adev, regSDMA0_EDC_COUNTER2, reg_value,
					      instance, &sec_count);

	/*
	 * err_data->ue_count should be initialized to 0
	 * before calling into this function
	 *
	 * SDMA RAS supports single bit uncorrectable error detection.
	 * So, increment uncorrectable error count.
	 */
	err_data->ue_count += sec_count;

	/*
	 * SDMA RAS does not support correctable errors.
	 * Set ce count to 0.
	 */
	err_data->ce_count = 0;

	return 0;
};

static void sdma_v4_4_reset_ras_error_count(struct amdgpu_device *adev)
{
	int i;
	uint32_t reg_offset;

	/* write 0 to EDC_COUNTER reg to clear sdma edc counters */
	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
		for (i = 0; i < adev->sdma.num_instances; i++) {
			reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER);
			WREG32(reg_offset, 0);
			reg_offset = sdma_v4_4_get_reg_offset(adev, i, regSDMA0_EDC_COUNTER2);
			WREG32(reg_offset, 0);
		}
	}
}

static void sdma_v4_4_query_ras_error_count(struct amdgpu_device *adev,  void *ras_error_status)
{
	int i = 0;

	for (i = 0; i < adev->sdma.num_instances; i++) {
		if (sdma_v4_4_query_ras_error_count_by_instance(adev, i, ras_error_status)) {
			dev_err(adev->dev, "Query ras error count failed in SDMA%d\n", i);
			return;
		}
	}

}

const struct amdgpu_ras_block_hw_ops sdma_v4_4_ras_hw_ops = {
	.query_ras_error_count = sdma_v4_4_query_ras_error_count,
	.reset_ras_error_count = sdma_v4_4_reset_ras_error_count,
};

struct amdgpu_sdma_ras sdma_v4_4_ras = {
	.ras_block = {
		.hw_ops = &sdma_v4_4_ras_hw_ops,
	},
};

Annotation

Implementation Notes