drivers/gpu/drm/amd/amdgpu/si_dma.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/si_dma.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/si_dma.c
Extension
.c
Size
23548 bytes
Lines
852
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (state) {
		case AMDGPU_IRQ_STATE_DISABLE:
			sdma_cntl = RREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET);
			sdma_cntl &= ~DMA_CNTL__TRAP_ENABLE_MASK;
			WREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);
			break;
		case AMDGPU_IRQ_STATE_ENABLE:
			sdma_cntl = RREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET);
			sdma_cntl |= DMA_CNTL__TRAP_ENABLE_MASK;
			WREG32(mmDMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);
			break;
		default:
			break;
		}
		break;
	case AMDGPU_SDMA_IRQ_INSTANCE1:
		switch (state) {
		case AMDGPU_IRQ_STATE_DISABLE:
			sdma_cntl = RREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET);
			sdma_cntl &= ~DMA_CNTL__TRAP_ENABLE_MASK;
			WREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);
			break;
		case AMDGPU_IRQ_STATE_ENABLE:
			sdma_cntl = RREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET);
			sdma_cntl |= DMA_CNTL__TRAP_ENABLE_MASK;
			WREG32(mmDMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl);
			break;
		default:
			break;
		}
		break;
	default:
		break;
	}
	return 0;
}

static int si_dma_process_trap_irq(struct amdgpu_device *adev,
				      struct amdgpu_irq_src *source,
				      struct amdgpu_iv_entry *entry)
{
	if (entry->src_id == 224)
		amdgpu_fence_process(&adev->sdma.instance[0].ring);
	else
		amdgpu_fence_process(&adev->sdma.instance[1].ring);
	return 0;
}

static int si_dma_set_clockgating_state(struct amdgpu_ip_block *ip_block,
					  enum amd_clockgating_state state)
{
	u32 orig, data, offset;
	int i;
	bool enable;
	struct amdgpu_device *adev = ip_block->adev;

	enable = (state == AMD_CG_STATE_GATE);

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
		for (i = 0; i < adev->sdma.num_instances; i++) {
			if (i == 0)
				offset = DMA0_REGISTER_OFFSET;
			else
				offset = DMA1_REGISTER_OFFSET;
			orig = data = RREG32(mmDMA_POWER_CNTL + offset);
			data &= ~DMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
			if (data != orig)
				WREG32(mmDMA_POWER_CNTL + offset, data);
			WREG32(mmDMA_CLK_CTRL + offset, 0x00000100);
		}
	} else {
		for (i = 0; i < adev->sdma.num_instances; i++) {
			if (i == 0)
				offset = DMA0_REGISTER_OFFSET;
			else
				offset = DMA1_REGISTER_OFFSET;
			orig = data = RREG32(mmDMA_POWER_CNTL + offset);
			data |= DMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
			if (data != orig)
				WREG32(mmDMA_POWER_CNTL + offset, data);

			orig = data = RREG32(mmDMA_CLK_CTRL + offset);
			data = 0xff000000;
			if (data != orig)
				WREG32(mmDMA_CLK_CTRL + offset, data);
		}
	}

	return 0;
}

Annotation

Implementation Notes