drivers/gpu/drm/amd/amdgpu/sid.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/sid.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/sid.h
Extension
.h
Size
31465 bytes
Lines
793
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef SI_H
#define SI_H

#define SI_MAX_CTLACKS_ASSERTION_WAIT   100

/* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */
#define SMC_CG_IND_START                    0xc0030000
#define SMC_CG_IND_END                      0xc0040000

/* SMC IND registers */
#define	SMC_SYSCON_RESET_CNTL				0x80000000
#       define RST_REG                                  (1 << 0)
#define	SMC_SYSCON_CLOCK_CNTL_0				0x80000004
#       define CK_DISABLE                               (1 << 0)
#       define CKEN                                     (1 << 24)

#define DCCG_DISP_SLOW_SELECT_REG                       0x13F
#define		DCCG_DISP1_SLOW_SELECT(x)		((x) << 0)
#define		DCCG_DISP1_SLOW_SELECT_MASK		(7 << 0)
#define		DCCG_DISP1_SLOW_SELECT_SHIFT		0
#define		DCCG_DISP2_SLOW_SELECT(x)		((x) << 4)
#define		DCCG_DISP2_SLOW_SELECT_MASK		(7 << 4)
#define		DCCG_DISP2_SLOW_SELECT_SHIFT		4

/* discrete uvd clocks */
#define	CG_UPLL_FUNC_CNTL				0x18d
#	define UPLL_RESET_MASK				0x00000001
#	define UPLL_SLEEP_MASK				0x00000002
#	define UPLL_BYPASS_EN_MASK			0x00000004
#	define UPLL_CTLREQ_MASK				0x00000008
#	define UPLL_VCO_MODE_MASK			0x00000600
#	define UPLL_REF_DIV_MASK			0x003F0000
#	define UPLL_CTLACK_MASK				0x40000000
#	define UPLL_CTLACK2_MASK			0x80000000
#define	CG_UPLL_FUNC_CNTL_2				0x18e
#	define UPLL_PDIV_A(x)				((x) << 0)
#	define UPLL_PDIV_A_MASK				0x0000007F
#	define UPLL_PDIV_B(x)				((x) << 8)
#	define UPLL_PDIV_B_MASK				0x00007F00
#	define VCLK_SRC_SEL(x)				((x) << 20)
#	define VCLK_SRC_SEL_MASK			0x01F00000
#	define DCLK_SRC_SEL(x)				((x) << 25)
#	define DCLK_SRC_SEL_MASK			0x3E000000
#define	CG_UPLL_FUNC_CNTL_3				0x18f
#	define UPLL_FB_DIV(x)				((x) << 0)
#	define UPLL_FB_DIV_MASK				0x01FFFFFF
#define	CG_UPLL_FUNC_CNTL_4                             0x191
#	define UPLL_SPARE_ISPARE9			0x00020000
#define	CG_UPLL_FUNC_CNTL_5				0x192
#	define RESET_ANTI_MUX_MASK			0x00000200
#define	CG_UPLL_SPREAD_SPECTRUM				0x194
#	define SSEN_MASK				0x00000001

#define VM_INVALIDATE_REQUEST				0x51E
#define VM_INVALIDATE_RESPONSE				0x51F

#define VM_L2_CG           				0x570
#define		MC_CG_ENABLE				(1 << 18)
#define		MC_LS_ENABLE				(1 << 19)

#define	MC_VM_FB_LOCATION				0x809
#define	MC_VM_AGP_TOP					0x80A
#define	MC_VM_AGP_BOT					0x80B
#define	MC_VM_AGP_BASE					0x80C
#define	MC_VM_SYSTEM_APERTURE_LOW_ADDR			0x80D
#define	MC_VM_SYSTEM_APERTURE_HIGH_ADDR			0x80E
#define	MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR		0x80F

#define	MC_VM_MX_L1_TLB_CNTL				0x819
#define		ENABLE_L1_TLB					(1 << 0)
#define		ENABLE_L1_FRAGMENT_PROCESSING			(1 << 1)
#define		SYSTEM_ACCESS_MODE_PA_ONLY			(0 << 3)
#define		SYSTEM_ACCESS_MODE_USE_SYS_MAP			(1 << 3)
#define		SYSTEM_ACCESS_MODE_IN_SYS			(2 << 3)
#define		SYSTEM_ACCESS_MODE_NOT_IN_SYS			(3 << 3)
#define		SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU	(0 << 5)
#define		ENABLE_ADVANCED_DRIVER_MODEL			(1 << 6)

#define MC_SHARED_BLACKOUT_CNTL           		0x82B

#define MC_HUB_MISC_HUB_CG           			0x82E
#define MC_HUB_MISC_VM_CG           			0x82F

#define MC_HUB_MISC_SIP_CG           			0x830

#define MC_XPB_CLK_GAT           			0x91E

#define MC_CITF_MISC_RD_CG           			0x992
#define MC_CITF_MISC_WR_CG           			0x993
#define MC_CITF_MISC_VM_CG           			0x994

Annotation

Implementation Notes