drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c
Extension
.c
Size
8104 bytes
Lines
297
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

for_each_handler(i, handler, reset_ctl) {
			if (handler->reset_method == reset_context->method)
				return handler;
		}
	}

	if (smu_v13_0_10_is_mode2_default(reset_ctl) &&
		amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_MODE2) {
		for_each_handler(i, handler, reset_ctl)	{
			if (handler->reset_method == AMD_RESET_METHOD_MODE2)
				return handler;
		}
	}

	return NULL;
}

static int smu_v13_0_10_mode2_suspend_ip(struct amdgpu_device *adev)
{
	int r, i;

	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);

	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
		if (!(adev->ip_blocks[i].version->type ==
			      AMD_IP_BLOCK_TYPE_GFX ||
		      adev->ip_blocks[i].version->type ==
			      AMD_IP_BLOCK_TYPE_SDMA ||
		      adev->ip_blocks[i].version->type ==
			      AMD_IP_BLOCK_TYPE_MES))
			continue;

		r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]);
		if (r)
			return r;
	}

	return 0;
}

static int
smu_v13_0_10_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
				  struct amdgpu_reset_context *reset_context)
{
	int r = 0;
	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;

	if (!amdgpu_sriov_vf(adev))
		r = smu_v13_0_10_mode2_suspend_ip(adev);

	return r;
}

static int smu_v13_0_10_mode2_reset(struct amdgpu_device *adev)
{
	return amdgpu_dpm_mode2_reset(adev);
}

static void smu_v13_0_10_async_reset(struct work_struct *work)
{
	struct amdgpu_reset_handler *handler;
	struct amdgpu_reset_control *reset_ctl =
		container_of(work, struct amdgpu_reset_control, reset_work);
	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
	int i;

	for_each_handler(i, handler, reset_ctl)	{
		if (handler->reset_method == reset_ctl->active_reset) {
			dev_dbg(adev->dev, "Resetting device\n");
			handler->do_reset(adev);
			break;
		}
	}
}
static int
smu_v13_0_10_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
			      struct amdgpu_reset_context *reset_context)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
	int r;

	r = smu_v13_0_10_mode2_reset(adev);
	if (r) {
		dev_err(adev->dev,
			"ASIC reset failed with error, %d ", r);
	}
	return r;
}

Annotation

Implementation Notes