drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.c- Extension
.c- Size
- 2777 bytes
- Lines
- 78
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu.hsmuio_v11_0_6.hsmuio/smuio_11_0_6_offset.hsmuio/smuio_11_0_6_sh_mask.h
Detected Declarations
function filesfunction smuio_v11_0_6_get_rom_data_offsetfunction smuio_v11_0_6_update_rom_clock_gatingfunction smuio_v11_0_6_get_clock_gating_state
Annotated Snippet
#include "amdgpu.h"
#include "smuio_v11_0_6.h"
#include "smuio/smuio_11_0_6_offset.h"
#include "smuio/smuio_11_0_6_sh_mask.h"
static u32 smuio_v11_0_6_get_rom_index_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
}
static u32 smuio_v11_0_6_get_rom_data_offset(struct amdgpu_device *adev)
{
return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
}
static void smuio_v11_0_6_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
{
u32 def, data;
/* enable/disable ROM CG is not supported on APU */
if (adev->flags & AMD_IS_APU)
return;
def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
else
data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
if (def != data)
WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data);
}
static void smuio_v11_0_6_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)
{
u32 data;
/* CGTT_ROM_CLK_CTRL0 is not available for APU */
if (adev->flags & AMD_IS_APU)
return;
data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
*flags |= AMD_CG_SUPPORT_ROM_MGCG;
}
const struct amdgpu_smuio_funcs smuio_v11_0_6_funcs = {
.get_rom_index_offset = smuio_v11_0_6_get_rom_index_offset,
.get_rom_data_offset = smuio_v11_0_6_get_rom_data_offset,
.update_rom_clock_gating = smuio_v11_0_6_update_rom_clock_gating,
.get_clock_gating_state = smuio_v11_0_6_get_clock_gating_state,
};
Annotation
- Immediate include surface: `amdgpu.h`, `smuio_v11_0_6.h`, `smuio/smuio_11_0_6_offset.h`, `smuio/smuio_11_0_6_sh_mask.h`.
- Detected declarations: `function files`, `function smuio_v11_0_6_get_rom_data_offset`, `function smuio_v11_0_6_update_rom_clock_gating`, `function smuio_v11_0_6_get_clock_gating_state`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.