drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c
Extension
.c
Size
6231 bytes
Lines
214
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include "amdgpu.h"
#include "smuio_v15_0_8.h"
#include "smuio/smuio_15_0_8_offset.h"
#include "smuio/smuio_15_0_8_sh_mask.h"

#define SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK	0x00000001L
#define SMUIO_MCM_CONFIG__ETHERNET_SWITCH_MASK	0x00000008L
#define SMUIO_MCM_CONFIG__CUSTOM_HBM_MASK	0x00000001L

static u32 smuio_v15_0_8_get_rom_index_offset(struct amdgpu_device *adev)
{
	return SOC15_REG_OFFSET(SMUIO, 0, regROM_INDEX);
}

static u32 smuio_v15_0_8_get_rom_data_offset(struct amdgpu_device *adev)
{
	return SOC15_REG_OFFSET(SMUIO, 0, regROM_DATA);
}

static void smuio_v15_0_8_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
{
	return;
}

static u64 smuio_v15_0_8_get_gpu_clock_counter(struct amdgpu_device *adev)
{
	u64 clock;
	u64 clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;

	preempt_disable();
	clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
	clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
	/* the clock counter may be udpated during polling the counters */
	clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
	if (clock_counter_hi_pre != clock_counter_hi_after)
		clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
	preempt_enable();

	clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);

	return clock;
}

static void smuio_v15_0_8_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags)
{
	u32 data;

	/* CGTT_ROM_CLK_CTRL0 is not available for APU */
	if (adev->flags & AMD_IS_APU)
		return;

	data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0);
	if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
		*flags |= AMD_CG_SUPPORT_ROM_MGCG;
}

/**
 * smuio_v15_0_8_get_die_id - query die id from FCH.
 *
 * @adev: amdgpu device pointer
 *
 * Returns die id
 */
static u32 smuio_v15_0_8_get_die_id(struct amdgpu_device *adev)
{
	u32 data, die_id;

	data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
	die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID);

	return die_id;
}

/**
 * smuio_v15_0_8_get_socket_id - query socket id from FCH
 *
 * @adev: amdgpu device pointer
 *
 * Returns socket id
 */
static u32 smuio_v15_0_8_get_socket_id(struct amdgpu_device *adev)
{
	u32 data, socket_id;

	data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG);
	socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID);

	return socket_id;
}

Annotation

Implementation Notes