drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/soc_v1_0.c- Extension
.c- Size
- 26425 bytes
- Lines
- 917
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu.hsoc15.hsoc15_common.hsoc_v1_0.hamdgpu_ip.hamdgpu_imu.hgfxhub_v12_1.hsdma_v7_1.hgfx_v12_1.hgc/gc_12_1_0_offset.hgc/gc_12_1_0_sh_mask.hmp/mp_15_0_8_offset.h
Detected Declarations
function soc_v1_0_query_video_codecsfunction soc_v1_0_doorbell_index_initfunction soc_v1_0_encode_ext_smn_addressingfunction soc_v1_0_get_config_memsizefunction soc_v1_0_get_xclkfunction soc_v1_0_grbm_selectfunction soc_v1_0_get_register_valuefunction soc_v1_0_read_registerfunction soc_v1_0_need_full_resetfunction soc_v1_0_need_reset_on_initfunction soc_v1_0_asic_reset_methodfunction soc_v1_0_asic_resetfunction soc_v1_0_common_early_initfunction soc_v1_0_common_late_initfunction soc_v1_0_common_sw_initfunction soc_v1_0_common_hw_initfunction soc_v1_0_common_hw_finifunction soc_v1_0_common_suspendfunction soc_v1_0_common_resumefunction soc_v1_0_common_is_idlefunction soc_v1_0_common_set_clockgating_statefunction soc_v1_0_common_set_powergating_statefunction soc_v1_0_common_get_clockgating_statefunction __soc_v1_0_calc_xcp_modefunction soc_v1_0_query_partition_modefunction __soc_v1_0_get_xcc_per_xcpfunction __soc_v1_0_get_xcp_ip_infofunction soc_v1_0_get_xcp_res_infofunction __soc_v1_0_get_auto_modefunction __soc_v1_0_is_valid_modefunction __soc_v1_0_update_available_partition_modefunction for_each_instfunction soc_v1_0_switch_partition_modefunction __soc_v1_0_get_xcp_mem_idfunction soc_v1_0_get_xcp_mem_idfunction soc_v1_0_get_xcp_ip_detailsfunction soc_v1_0_xcp_mgr_initfunction soc_v1_0_init_soc_configfunction soc_v1_0_normalize_xcc_reg_rangefunction soc_v1_0_normalize_xcc_reg_offsetfunction soc_v1_0_mid1_reg_rangefunction soc_v1_0_normalize_reg_offset
Annotated Snippet
if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) {
dev_err(adev->dev,
"Invalid config, no compatible compute partition mode found, available memory partitions: %d",
adev->gmc.num_mem_partitions);
return -EINVAL;
}
} else if (!__soc_v1_0_is_valid_mode(xcp_mgr, mode)) {
dev_err(adev->dev,
"Invalid compute partition mode requested, requested: %s, available memory partitions: %d",
amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions);
return -EINVAL;
}
if (adev->kfd.init_complete && !amdgpu_in_reset(adev))
flags |= AMDGPU_XCP_OPS_KFD;
if (flags & AMDGPU_XCP_OPS_KFD) {
ret = amdgpu_amdkfd_check_and_lock_kfd(adev);
if (ret)
goto out;
}
ret = amdgpu_xcp_pre_partition_switch(xcp_mgr, flags);
if (ret)
goto unlock;
num_xcc_per_xcp = __soc_v1_0_get_xcc_per_xcp(xcp_mgr, mode);
if (adev->gfx.imu.funcs &&
adev->gfx.imu.funcs->switch_compute_partition)
adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode);
/* Init info about new xcps */
*num_xcps = num_xcc / num_xcc_per_xcp;
amdgpu_xcp_init(xcp_mgr, *num_xcps, mode);
ret = amdgpu_xcp_post_partition_switch(xcp_mgr, flags);
if (!ret)
__soc_v1_0_update_available_partition_mode(xcp_mgr);
unlock:
if (flags & AMDGPU_XCP_OPS_KFD)
amdgpu_amdkfd_unlock_kfd(adev);
out:
return ret;
}
#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV
static int __soc_v1_0_get_xcp_mem_id(struct amdgpu_device *adev,
int xcc_id, uint8_t *mem_id)
{
/* memory/spatial modes validation check is already done */
*mem_id = xcc_id / adev->gfx.num_xcc_per_xcp;
*mem_id /= adev->xcp_mgr->num_xcp_per_mem_partition;
return 0;
}
static int soc_v1_0_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr,
struct amdgpu_xcp *xcp, uint8_t *mem_id)
{
struct amdgpu_numa_info numa_info;
struct amdgpu_device *adev;
uint32_t xcc_mask;
int r, i, xcc_id;
adev = xcp_mgr->adev;
/* TODO: BIOS is not returning the right info now
* Check on this later
*/
/*
if (adev->gmc.gmc_funcs->query_mem_partition_mode)
mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
*/
if (adev->gmc.num_mem_partitions == 1) {
/* Only one range */
*mem_id = 0;
return 0;
}
r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask);
if (r || !xcc_mask)
return -EINVAL;
xcc_id = ffs(xcc_mask) - 1;
if (!adev->gmc.is_app_apu)
return __soc_v1_0_get_xcp_mem_id(adev, xcc_id, mem_id);
r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info);
if (r)
return r;
Annotation
- Immediate include surface: `amdgpu.h`, `soc15.h`, `soc15_common.h`, `soc_v1_0.h`, `amdgpu_ip.h`, `amdgpu_imu.h`, `gfxhub_v12_1.h`, `sdma_v7_1.h`.
- Detected declarations: `function soc_v1_0_query_video_codecs`, `function soc_v1_0_doorbell_index_init`, `function soc_v1_0_encode_ext_smn_addressing`, `function soc_v1_0_get_config_memsize`, `function soc_v1_0_get_xclk`, `function soc_v1_0_grbm_select`, `function soc_v1_0_get_register_value`, `function soc_v1_0_read_register`, `function soc_v1_0_need_full_reset`, `function soc_v1_0_need_reset_on_init`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.