drivers/gpu/drm/amd/amdgpu/soc15.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/soc15.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/soc15.c
Extension
.c
Size
45894 bytes
Lines
1496
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) {
		case IP_VERSION(4, 0, 0):
		case IP_VERSION(4, 1, 0):
			if (encode)
				*codecs = &vega_video_codecs_encode;
			else
				*codecs = &vega_video_codecs_decode;
			return 0;
		default:
			return -EINVAL;
		}
	} else {
		switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) {
		case IP_VERSION(1, 0, 0):
		case IP_VERSION(1, 0, 1):
			if (encode)
				*codecs = &vega_video_codecs_encode;
			else
				*codecs = &rv_video_codecs_decode;
			return 0;
		case IP_VERSION(2, 5, 0):
		case IP_VERSION(2, 6, 0):
		case IP_VERSION(2, 2, 0):
			if (encode)
				*codecs = &vega_video_codecs_encode;
			else
				*codecs = &rn_video_codecs_decode;
			return 0;
		case IP_VERSION(4, 0, 3):
			if (encode)
				*codecs = &vcn_4_0_3_video_codecs_encode;
			else
				*codecs = &vcn_4_0_3_video_codecs_decode;
			return 0;
		case IP_VERSION(5, 0, 1):
			if (encode)
				*codecs = &vcn_5_0_1_video_codecs_encode_vcn0;
			else
				*codecs = &vcn_5_0_1_video_codecs_decode_vcn0;
			return 0;
		default:
			return -EINVAL;
		}
	}
}

static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
{
	unsigned long flags, address, data;
	u32 r;

	address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
	data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);

	spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags);
	WREG32(address, ((reg) & 0x1ff));
	r = RREG32(data);
	spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags);
	return r;
}

static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{
	unsigned long flags, address, data;

	address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
	data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);

	spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags);
	WREG32(address, ((reg) & 0x1ff));
	WREG32(data, (v));
	spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags);
}

static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg)
{
	unsigned long flags, address, data;
	u32 r;

	address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
	data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);

	spin_lock_irqsave(&adev->reg.didt.lock, flags);
	WREG32(address, (reg));
	r = RREG32(data);
	spin_unlock_irqrestore(&adev->reg.didt.lock, flags);
	return r;
}

static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)

Annotation

Implementation Notes