drivers/gpu/drm/amd/amdgpu/soc21.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/soc21.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/soc21.c
Extension
.c
Size
34035 bytes
Lines
1057
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (amdgpu_sriov_vf(adev)) {
			if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
			!amdgpu_sriov_is_av1_support(adev)) {
				if (encode)
					*codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
				else
					*codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
			} else {
				if (encode)
					*codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
				else
					*codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
			}
		} else {
			if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
				if (encode)
					*codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
				else
					*codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
			} else {
				if (encode)
					*codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
				else
					*codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
			}
		}
		return 0;
	case IP_VERSION(4, 0, 6):
		if (encode)
			*codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
		else
			*codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
		return 0;
	case IP_VERSION(5, 3, 0):
		if (encode)
			*codecs = &vcn_5_3_0_video_codecs_encode_vcn0;
		else
			*codecs = &vcn_5_3_0_video_codecs_decode_vcn0;
		return 0;
	default:
		return -EINVAL;
	}
}

static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
{
	unsigned long flags, address, data;
	u32 r;

	address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
	data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);

	spin_lock_irqsave(&adev->reg.didt.lock, flags);
	WREG32(address, (reg));
	r = RREG32(data);
	spin_unlock_irqrestore(&adev->reg.didt.lock, flags);
	return r;
}

static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
{
	unsigned long flags, address, data;

	address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
	data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);

	spin_lock_irqsave(&adev->reg.didt.lock, flags);
	WREG32(address, (reg));
	WREG32(data, (v));
	spin_unlock_irqrestore(&adev->reg.didt.lock, flags);
}

static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
{
	return adev->nbio.funcs->get_memsize(adev);
}

static u32 soc21_get_xclk(struct amdgpu_device *adev)
{
	u32 reference_clock = adev->clock.spll.reference_freq;

	/* reference clock is actually 99.81 Mhz rather than 100 Mhz */
	if ((adev->flags & AMD_IS_APU) && reference_clock == 10000)
		return 9981;

	return reference_clock;
}


void soc21_grbm_select(struct amdgpu_device *adev,

Annotation

Implementation Notes