drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/ta_ras_if.h- Extension
.h- Size
- 6812 bytes
- Lines
- 225
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct ta_ras_enable_features_inputstruct ta_ras_disable_features_inputstruct ta_ras_trigger_error_inputstruct ta_ras_init_flagsstruct ta_ras_mca_addrstruct ta_ras_phy_addrstruct ta_ras_query_address_inputstruct ta_ras_output_flagsstruct ta_ras_query_address_outputstruct ta_ras_shared_memoryenum ras_commandenum ta_ras_statusenum ta_ras_blockenum ta_ras_mca_blockenum ta_ras_error_typeenum ta_ras_address_typeenum ta_ras_nps_mode
Annotated Snippet
struct ta_ras_enable_features_input {
enum ta_ras_block block_id;
enum ta_ras_error_type error_type;
};
struct ta_ras_disable_features_input {
enum ta_ras_block block_id;
enum ta_ras_error_type error_type;
};
struct ta_ras_trigger_error_input {
enum ta_ras_block block_id; // ras-block. i.e. umc, gfx
enum ta_ras_error_type inject_error_type; // type of error. i.e. single_correctable
uint32_t sub_block_index; // mem block. i.e. hbm, sram etc.
uint64_t address; // explicit address of error
uint64_t value; // method if error injection. i.e persistent, coherent etc.
};
struct ta_ras_init_flags {
uint8_t poison_mode_en;
uint8_t dgpu_mode;
uint16_t xcc_mask;
uint8_t channel_dis_num;
uint8_t nps_mode;
uint32_t active_umc_mask;
uint8_t vram_type;
};
struct ta_ras_mca_addr {
uint64_t err_addr;
uint32_t ch_inst;
uint32_t umc_inst;
uint32_t node_inst;
uint32_t socket_id;
};
struct ta_ras_phy_addr {
uint64_t pa;
uint32_t bank;
uint32_t channel_idx;
};
struct ta_ras_query_address_input {
enum ta_ras_address_type addr_type;
struct ta_ras_mca_addr ma;
struct ta_ras_phy_addr pa;
};
struct ta_ras_output_flags {
uint8_t ras_init_success_flag;
uint8_t err_inject_switch_disable_flag;
uint8_t reg_access_failure_flag;
};
struct ta_ras_query_address_output {
/* don't use the flags here */
struct ta_ras_output_flags flags;
struct ta_ras_mca_addr ma;
struct ta_ras_phy_addr pa;
};
/* Common input structure for RAS callbacks */
/**********************************************************/
union ta_ras_cmd_input {
struct ta_ras_init_flags init_flags;
struct ta_ras_enable_features_input enable_features;
struct ta_ras_disable_features_input disable_features;
struct ta_ras_trigger_error_input trigger_error;
struct ta_ras_query_address_input address;
uint32_t reserve_pad[256];
};
union ta_ras_cmd_output {
struct ta_ras_output_flags flags;
struct ta_ras_query_address_output address;
uint32_t reserve_pad[256];
};
/* Shared Memory structures */
/**********************************************************/
struct ta_ras_shared_memory {
uint32_t cmd_id;
uint32_t resp_id;
uint32_t ras_status;
uint32_t if_version;
union ta_ras_cmd_input ras_in_message;
union ta_ras_cmd_output ras_out_message;
};
Annotation
- Detected declarations: `struct ta_ras_enable_features_input`, `struct ta_ras_disable_features_input`, `struct ta_ras_trigger_error_input`, `struct ta_ras_init_flags`, `struct ta_ras_mca_addr`, `struct ta_ras_phy_addr`, `struct ta_ras_query_address_input`, `struct ta_ras_output_flags`, `struct ta_ras_query_address_output`, `struct ta_ras_shared_memory`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.