drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/umc_v12_0.c
Extension
.c
Size
25093 bytes
Lines
791
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (nps == AMDGPU_NPS2_PARTITION_MODE) {
			flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;
			flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;
			flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;
			flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;
		} else if (nps == AMDGPU_NPS4_PARTITION_MODE) {
			flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
			flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
			flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
			flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;
		}

		switch (vram_type) {
		case AMDGPU_VRAM_TYPE_HBM:
			/* other nps modes are taken as nps1 */
			if (nps == AMDGPU_NPS2_PARTITION_MODE)
				flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
			else if (nps == AMDGPU_NPS4_PARTITION_MODE)
				flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;

			break;
		case AMDGPU_VRAM_TYPE_HBM3E:
			flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;
			flip_bits->flip_row_bit = 12;

			if (nps == AMDGPU_NPS2_PARTITION_MODE)
				flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
			else if (nps == AMDGPU_NPS4_PARTITION_MODE)
				flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT;

			break;
		default:
			dev_warn(adev->dev,
				"Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n");
			break;
		}
	} else if (adev->gmc.num_umc == 8) {
		/* default setting */
		flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT;
		flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT;
		flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT;
		flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
		flip_bits->flip_row_bit = 12;
		flip_bits->bit_num = 4;
		flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT;

		if (nps == AMDGPU_NPS2_PARTITION_MODE) {
			flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT;
			flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT;
			flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT;
			flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT;
		}

		switch (vram_type) {
		case AMDGPU_VRAM_TYPE_HBM:
			flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT;

			/* other nps modes are taken as nps1 */
			if (nps == AMDGPU_NPS2_PARTITION_MODE)
				flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;

			break;
		case AMDGPU_VRAM_TYPE_HBM3E:
			flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT;
			flip_bits->flip_row_bit = 12;

			if (nps == AMDGPU_NPS2_PARTITION_MODE)
				flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT;

			break;
		default:
			dev_warn(adev->dev,
				"Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n");
			break;
		}
	} else {
		dev_warn(adev->dev,
			"Unsupported UMC number(%d), failed to set RAS flip bits.\n",
			adev->gmc.num_umc);

		return;
	}

	adev->umc.retire_unit = 0x1 << flip_bits->bit_num;
}

static int umc_v12_0_convert_error_address(struct amdgpu_device *adev,
					struct ras_err_data *err_data,
					struct ta_ras_query_address_input *addr_in,
					struct ta_ras_query_address_output *addr_out,

Annotation

Implementation Notes