drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/umc_v6_7.c
Extension
.c
Size
17956 bytes
Lines
529
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1) {
		*error_count += 1;

		umc_v6_7_query_error_status_helper(adev, mc_umc_status, umc_reg_offset);

		if (ras->umc_ecc.record_ce_addr_supported)	{
			uint64_t err_addr, soc_pa;
			uint32_t channel_index =
				adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];

			err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr;
			err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr);
			/* translate umc channel address to soc pa, 3 parts are included */
			soc_pa = ADDR_OF_8KB_BLOCK(err_addr) |
					ADDR_OF_256B_BLOCK(channel_index) |
					OFFSET_IN_256B_BLOCK(err_addr);

			/* The umc channel bits are not original values, they are hashed */
			SET_CHANNEL_HASH(channel_index, soc_pa);

			dev_info(adev->dev, "Error Address(PA): 0x%llx\n", soc_pa);
		}
	}
}

static void umc_v6_7_ecc_info_querry_uncorrectable_error_count(struct amdgpu_device *adev,
							  uint32_t umc_inst, uint32_t ch_inst,
						      unsigned long *error_count)
{
	uint64_t mc_umc_status;
	uint32_t eccinfo_table_idx;
	uint32_t umc_reg_offset;
	struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);

	umc_reg_offset = get_umc_v6_7_reg_offset(adev,
						umc_inst, ch_inst);

	eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
	/* check the MCUMC_STATUS */
	mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status;
	if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1)) {
		*error_count += 1;

		umc_v6_7_query_error_status_helper(adev, mc_umc_status, umc_reg_offset);
	}
}

static int umc_v6_7_ecc_info_querry_ecc_error_count(struct amdgpu_device *adev,
					uint32_t node_inst, uint32_t umc_inst,
					uint32_t ch_inst, void *data)
{
	struct ras_err_data *err_data = (struct ras_err_data *)data;

	umc_v6_7_ecc_info_query_correctable_error_count(adev,
		umc_inst, ch_inst,
		&(err_data->ce_count));

	umc_v6_7_ecc_info_querry_uncorrectable_error_count(adev,
		umc_inst, ch_inst,
		&(err_data->ue_count));

	return 0;
}

static void umc_v6_7_ecc_info_query_ras_error_count(struct amdgpu_device *adev,
					   void *ras_error_status)
{
	amdgpu_umc_loop_channels(adev,
		umc_v6_7_ecc_info_querry_ecc_error_count, ras_error_status);
}

void umc_v6_7_convert_error_address(struct amdgpu_device *adev,
				    struct ras_err_data *err_data, uint64_t err_addr,
				    uint32_t ch_inst, uint32_t umc_inst)
{
	uint32_t channel_index;
	uint64_t soc_pa, retired_page, column;

	channel_index =
		adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
	/* translate umc channel address to soc pa, 3 parts are included */
	soc_pa = ADDR_OF_8KB_BLOCK(err_addr) |
			ADDR_OF_256B_BLOCK(channel_index) |
			OFFSET_IN_256B_BLOCK(err_addr);

Annotation

Implementation Notes