drivers/gpu/drm/amd/amdgpu/umc_v8_7.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/umc_v8_7.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/umc_v8_7.h
Extension
.h
Size
2153 bytes
Lines
52
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __UMC_V8_7_H__
#define __UMC_V8_7_H__

#include "soc15_common.h"
#include "amdgpu.h"

/* HBM  Memory Channel Width */
#define UMC_V8_7_HBM_MEMORY_CHANNEL_WIDTH	128
/* number of umc channel instance with memory map register access */
#define UMC_V8_7_CHANNEL_INSTANCE_NUM		2
/* number of umc instance with memory map register access */
#define UMC_V8_7_UMC_INSTANCE_NUM		8
/* total channel instances in one umc block */
#define UMC_V8_7_TOTAL_CHANNEL_NUM	(UMC_V8_7_CHANNEL_INSTANCE_NUM * UMC_V8_7_UMC_INSTANCE_NUM)
/* UMC regiser per channel offset */
#define UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA	0x400

/* EccErrCnt max value */
#define UMC_V8_7_CE_CNT_MAX		0xffff
/* umc ce interrupt threshold */
#define UMC_V8_7_CE_INT_THRESHOLD	0xffff
/* umc ce count initial value */
#define UMC_V8_7_CE_CNT_INIT	(UMC_V8_7_CE_CNT_MAX - UMC_V8_7_CE_INT_THRESHOLD)

extern struct amdgpu_umc_ras umc_v8_7_ras;
extern const uint32_t
	umc_v8_7_channel_idx_tbl[UMC_V8_7_UMC_INSTANCE_NUM][UMC_V8_7_CHANNEL_INSTANCE_NUM];

#endif

Annotation

Implementation Notes