drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
Extension
.c
Size
16255 bytes
Lines
435
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <linux/firmware.h>
#include <linux/module.h>
#include <linux/debugfs.h>
#include "amdgpu.h"
#include "soc15_common.h"
#include "soc21.h"
#include "vcn/vcn_4_0_0_offset.h"
#include "vcn/vcn_4_0_0_sh_mask.h"

#include "amdgpu_umsch_mm.h"
#include "umsch_mm_4_0_api_def.h"
#include "umsch_mm_v4_0.h"

#define regUVD_IPX_DLDO_CONFIG                             0x0064
#define regUVD_IPX_DLDO_CONFIG_BASE_IDX                    1
#define regUVD_IPX_DLDO_STATUS                             0x0065
#define regUVD_IPX_DLDO_STATUS_BASE_IDX                    1

#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT        0x00000002
#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK          0x0000000cUL
#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT        0x00000001
#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK          0x00000002UL

static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)
{
	struct amdgpu_device *adev = umsch->ring.adev;
	uint64_t data;
	int r;

	r = amdgpu_umsch_mm_allocate_ucode_buffer(umsch);
	if (r)
		return r;

	r = amdgpu_umsch_mm_allocate_ucode_data_buffer(umsch);
	if (r)
		goto err_free_ucode_bo;

	umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;

	if (amdgpu_ip_version(adev, VCN_HWIP, 0) >= IP_VERSION(4, 0, 5)) {
		WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
			1 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
		SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
			0 << UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
			UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
	}

	data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
	data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL, MES_CORE_SOFT_RESET, 0);
	WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data);

	data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);
	data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 1);
	data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 1);
	data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 0);
	data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 1);
	WREG32_SOC15_UMSCH(regVCN_MES_CNTL, data);

	data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_BASE_CNTL);
	data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, VMID, 0);
	data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, EXE_DISABLE, 0);
	data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, CACHE_POLICY, 0);
	WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_CNTL, data);

	WREG32_SOC15_UMSCH(regVCN_MES_INTR_ROUTINE_START,
		lower_32_bits(adev->umsch_mm.irq_start_addr >> 2));

Annotation

Implementation Notes