drivers/gpu/drm/amd/amdgpu/vce_v1_0.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/vce_v1_0.c- Extension
.c- Size
- 22420 bytes
- Lines
- 855
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/firmware.hamdgpu.hamdgpu_vce.hamdgpu_gart.hsid.hvce_v1_0.hvce/vce_1_0_d.hvce/vce_1_0_sh_mask.hoss/oss_1_0_d.hoss/oss_1_0_sh_mask.h
Detected Declarations
struct vce_v1_0_fw_signaturefunction vce_v1_0_ring_get_rptrfunction vce_v1_0_ring_get_wptrfunction vce_v1_0_ring_set_wptrfunction vce_v1_0_lmi_cleanfunction vce_v1_0_firmware_loadedfunction vce_v1_0_init_cgfunction vce_v1_0_load_fwfunction vce_v1_0_wait_for_fw_validationfunction vce_v1_0_mc_resumefunction vce_v1_0_is_idlefunction vce_v1_0_wait_for_idlefunction vce_v1_0_startfunction vce_v1_0_stopfunction vce_v1_0_enable_mgcgfunction vce_v1_0_early_initfunction vce_v1_0_ensure_vcpu_bo_32bit_addrfunction vce_v1_0_sw_initfunction vce_v1_0_sw_finifunction vce_v1_0_hw_initfunction vce_v1_0_hw_finifunction vce_v1_0_suspendfunction vce_v1_0_resumefunction vce_v1_0_set_interrupt_statefunction vce_v1_0_process_interruptfunction vce_v1_0_set_clockgating_statefunction vce_v1_0_set_powergating_statefunction vce_v1_0_set_ring_funcsfunction vce_v1_0_set_irq_funcs
Annotated Snippet
struct vce_v1_0_fw_signature {
int32_t offset;
uint32_t length;
int32_t number;
struct {
uint32_t chip_id;
uint32_t keyselect;
uint32_t nonce[4];
uint32_t sigval[4];
} val[8];
};
/**
* vce_v1_0_ring_get_rptr - get read pointer
*
* @ring: amdgpu_ring pointer
*
* Returns the current hardware read pointer
*/
static uint64_t vce_v1_0_ring_get_rptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
if (ring->me == 0)
return RREG32(mmVCE_RB_RPTR);
else
return RREG32(mmVCE_RB_RPTR2);
}
/**
* vce_v1_0_ring_get_wptr - get write pointer
*
* @ring: amdgpu_ring pointer
*
* Returns the current hardware write pointer
*/
static uint64_t vce_v1_0_ring_get_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
if (ring->me == 0)
return RREG32(mmVCE_RB_WPTR);
else
return RREG32(mmVCE_RB_WPTR2);
}
/**
* vce_v1_0_ring_set_wptr - set write pointer
*
* @ring: amdgpu_ring pointer
*
* Commits the write pointer to the hardware
*/
static void vce_v1_0_ring_set_wptr(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
if (ring->me == 0)
WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
else
WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
}
static int vce_v1_0_lmi_clean(struct amdgpu_device *adev)
{
int i, j;
for (i = 0; i < 10; ++i) {
for (j = 0; j < 100; ++j) {
if (RREG32(mmVCE_LMI_STATUS) & 0x337f)
return 0;
mdelay(10);
}
}
return -ETIMEDOUT;
}
static int vce_v1_0_firmware_loaded(struct amdgpu_device *adev)
{
int i, j;
for (i = 0; i < 10; ++i) {
for (j = 0; j < 100; ++j) {
if (RREG32(mmVCE_STATUS) & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
return 0;
mdelay(10);
}
Annotation
- Immediate include surface: `linux/firmware.h`, `amdgpu.h`, `amdgpu_vce.h`, `amdgpu_gart.h`, `sid.h`, `vce_v1_0.h`, `vce/vce_1_0_d.h`, `vce/vce_1_0_sh_mask.h`.
- Detected declarations: `struct vce_v1_0_fw_signature`, `function vce_v1_0_ring_get_rptr`, `function vce_v1_0_ring_get_wptr`, `function vce_v1_0_ring_set_wptr`, `function vce_v1_0_lmi_clean`, `function vce_v1_0_firmware_loaded`, `function vce_v1_0_init_cg`, `function vce_v1_0_load_fw`, `function vce_v1_0_wait_for_fw_validation`, `function vce_v1_0_mc_resume`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.