drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
Extension
.c
Size
69971 bytes
Lines
2280
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (r) {
			dev_err(adev->dev, "Failed to initialize vcn ras block!\n");
			return r;
		}
	}

	r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_4_0_3, ARRAY_SIZE(vcn_reg_list_4_0_3));
	if (r)
		return r;

	return amdgpu_vcn_sysfs_reset_mask_init(adev);
}

/**
 * vcn_v4_0_3_sw_fini - sw fini for VCN block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * VCN suspend and free up sw allocation
 */
static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block)
{
	struct amdgpu_device *adev = ip_block->adev;
	int i, r, idx;

	if (drm_dev_enter(&adev->ddev, &idx)) {
		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
			struct amdgpu_vcn4_fw_shared *fw_shared;

			fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
			fw_shared->present_flag_0 = 0;
			fw_shared->sq.is_enabled = cpu_to_le32(false);
		}
		drm_dev_exit(idx);
	}

	if (amdgpu_sriov_vf(adev))
		amdgpu_virt_free_mm_table(adev);

	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
		r = amdgpu_vcn_suspend(adev, i);
		if (r)
			return r;
	}

	amdgpu_vcn_sysfs_reset_mask_fini(adev);

	for (i = 0; i < adev->vcn.num_vcn_inst; i++)
		amdgpu_vcn_sw_fini(adev, i);

	return 0;
}

static int vcn_v4_0_3_hw_init_inst(struct amdgpu_vcn_inst *vinst)
{
	int vcn_inst;
	struct amdgpu_device *adev = vinst->adev;
	struct amdgpu_ring *ring;
	int inst_idx = vinst->inst;

	vcn_inst = GET_INST(VCN, inst_idx);
	ring = &adev->vcn.inst[inst_idx].ring_enc[0];
	if (ring->use_doorbell) {
		adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
			(adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 9 * vcn_inst,
			adev->vcn.inst[inst_idx].aid_id);

		WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL,
			ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
			VCN_RB1_DB_CTRL__EN_MASK);

		/* Read DB_CTRL to flush the write DB_CTRL command. */
		RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL);
	}

	return 0;
}

/**
 * vcn_v4_0_3_hw_init - start and test VCN block
 *
 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
 *
 * Initialize the hardware, boot up the VCPU and do some testing
 */
static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block)
{
	struct amdgpu_device *adev = ip_block->adev;
	struct amdgpu_ring *ring;
	struct amdgpu_vcn_inst *vinst;

Annotation

Implementation Notes