drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.h

Extension

.h

Size

1637 bytes

Lines

38

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __VCN_V5_0_0_H__
#define __VCN_V5_0_0_H__

#define VCN_VID_SOC_ADDRESS                        0x1FC00
#define VCN_AON_SOC_ADDRESS                        0x1F800
#define VCN1_VID_SOC_ADDRESS                       0x48300
#define VCN1_AON_SOC_ADDRESS                       0x48000

#define VCN_VID_IP_ADDRESS                         0x0
#define VCN_AON_IP_ADDRESS                         0x30000

extern const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block;

#endif /* __VCN_V5_0_0_H__ */

Annotation

• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.