drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c- Extension
.c- Size
- 54875 bytes
- Lines
- 1820
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/firmware.hamdgpu.hamdgpu_vcn.hamdgpu_pm.hsoc15.hsoc15d.hsoc15_hw_ip.hvcn_v2_0.hvcn_v4_0_3.hmmsch_v5_0.hvcn/vcn_5_0_0_offset.hvcn/vcn_5_0_0_sh_mask.hivsrcid/vcn/irqsrcs_vcn_5_0.hvcn_v5_0_0.hvcn_v5_0_1.hdrm/drm_drv.h
Detected Declarations
function vcn_v5_0_1_early_initfunction vcn_v5_0_1_late_initfunction vcn_v5_0_1_fw_shared_initfunction vcn_v5_0_1_sw_initfunction vcn_v5_0_1_sw_finifunction vcn_v5_0_1_hw_init_instfunction vcn_v5_0_1_hw_initfunction vcn_v5_0_1_hw_finifunction vcn_v5_0_1_suspendfunction vcn_v5_0_1_resumefunction vcn_v5_0_1_mc_resumefunction vcn_v5_0_1_mc_resume_dpg_modefunction vcn_v5_0_1_disable_clock_gatingfunction vcn_v5_0_1_start_dpg_modefunction vcn_v5_0_1_start_sriovfunction vcn_v5_0_1_startfunction vcn_v5_0_1_stop_dpg_modefunction vcn_v5_0_1_stopfunction vcn_v5_0_1_unified_ring_get_rptrfunction vcn_v5_0_1_unified_ring_get_wptrfunction vcn_v5_0_1_unified_ring_set_wptrfunction vcn_v5_0_1_reset_jpeg_pre_helperfunction vcn_v5_0_1_reset_jpeg_post_helperfunction vcn_v5_0_1_ring_resetfunction vcn_v5_0_1_set_unified_ring_funcsfunction vcn_v5_0_1_is_idlefunction vcn_v5_0_1_wait_for_idlefunction vcn_v5_0_1_set_clockgating_statefunction vcn_v5_0_1_set_pg_statefunction vcn_v5_0_1_process_interruptfunction vcn_v5_0_1_set_ras_interrupt_statefunction vcn_v5_0_1_set_irq_funcsfunction vcn_v5_0_1_query_poison_by_instancefunction vcn_v5_0_1_query_poison_statusfunction vcn_v5_0_1_aca_bank_parserfunction vcn_v5_0_1_aca_bank_is_validfunction vcn_v5_0_1_ras_late_initfunction vcn_v5_0_1_set_ras_funcs
Annotated Snippet
if (r) {
dev_err(adev->dev, "Failed to initialize vcn ras block!\n");
return r;
}
}
r = amdgpu_vcn_reg_dump_init(adev, vcn_reg_list_5_0_1, ARRAY_SIZE(vcn_reg_list_5_0_1));
if (r)
return r;
return amdgpu_vcn_sysfs_reset_mask_init(adev);
}
/**
* vcn_v5_0_1_sw_fini - sw fini for VCN block
*
* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
*
* VCN suspend and free up sw allocation
*/
static int vcn_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
int i, r, idx;
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
struct amdgpu_vcn5_fw_shared *fw_shared;
fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
fw_shared->present_flag_0 = 0;
fw_shared->sq.is_enabled = 0;
}
drm_dev_exit(idx);
}
if (amdgpu_sriov_vf(adev))
amdgpu_virt_free_mm_table(adev);
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
r = amdgpu_vcn_suspend(adev, i);
if (r)
return r;
}
amdgpu_vcn_sysfs_reset_mask_fini(adev);
for (i = 0; i < adev->vcn.num_vcn_inst; i++)
amdgpu_vcn_sw_fini(adev, i);
return 0;
}
static int vcn_v5_0_1_hw_init_inst(struct amdgpu_device *adev, int i)
{
struct amdgpu_ring *ring;
int vcn_inst;
vcn_inst = GET_INST(VCN, i);
ring = &adev->vcn.inst[i].ring_enc[0];
if (ring->use_doorbell)
adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
((adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
11 * vcn_inst),
adev->vcn.inst[i].aid_id);
return 0;
}
/**
* vcn_v5_0_1_hw_init - start and test VCN block
*
* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
*
* Initialize the hardware, boot up the VCPU and do some testing
*/
static int vcn_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_ring *ring;
int i, r;
if (amdgpu_sriov_vf(adev)) {
r = vcn_v5_0_1_start_sriov(adev);
if (r)
return r;
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
Annotation
- Immediate include surface: `linux/firmware.h`, `amdgpu.h`, `amdgpu_vcn.h`, `amdgpu_pm.h`, `soc15.h`, `soc15d.h`, `soc15_hw_ip.h`, `vcn_v2_0.h`.
- Detected declarations: `function vcn_v5_0_1_early_init`, `function vcn_v5_0_1_late_init`, `function vcn_v5_0_1_fw_shared_init`, `function vcn_v5_0_1_sw_init`, `function vcn_v5_0_1_sw_fini`, `function vcn_v5_0_1_hw_init_inst`, `function vcn_v5_0_1_hw_init`, `function vcn_v5_0_1_hw_fini`, `function vcn_v5_0_1_suspend`, `function vcn_v5_0_1_resume`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.