drivers/gpu/drm/amd/amdgpu/vid.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/vid.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/vid.h
Extension
.h
Size
19347 bytes
Lines
516
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef VI_H
#define VI_H

#define SDMA0_REGISTER_OFFSET                             0x0 /* not a register */
#define SDMA1_REGISTER_OFFSET                             0x200 /* not a register */
#define SDMA_MAX_INSTANCE 2

#define KFD_VI_SDMA_QUEUE_OFFSET                      0x80 /* not a register */

/* crtc instance offsets */
#define CRTC0_REGISTER_OFFSET                 (0x1b9c - 0x1b9c)
#define CRTC1_REGISTER_OFFSET                 (0x1d9c - 0x1b9c)
#define CRTC2_REGISTER_OFFSET                 (0x1f9c - 0x1b9c)
#define CRTC3_REGISTER_OFFSET                 (0x419c - 0x1b9c)
#define CRTC4_REGISTER_OFFSET                 (0x439c - 0x1b9c)
#define CRTC5_REGISTER_OFFSET                 (0x459c - 0x1b9c)
#define CRTC6_REGISTER_OFFSET                 (0x479c - 0x1b9c)

/* dig instance offsets */
#define DIG0_REGISTER_OFFSET                 (0x4a00 - 0x4a00)
#define DIG1_REGISTER_OFFSET                 (0x4b00 - 0x4a00)
#define DIG2_REGISTER_OFFSET                 (0x4c00 - 0x4a00)
#define DIG3_REGISTER_OFFSET                 (0x4d00 - 0x4a00)
#define DIG4_REGISTER_OFFSET                 (0x4e00 - 0x4a00)
#define DIG5_REGISTER_OFFSET                 (0x4f00 - 0x4a00)
#define DIG6_REGISTER_OFFSET                 (0x5400 - 0x4a00)
#define DIG7_REGISTER_OFFSET                 (0x5600 - 0x4a00)
#define DIG8_REGISTER_OFFSET                 (0x5700 - 0x4a00)

/* audio endpt instance offsets */
#define AUD0_REGISTER_OFFSET                 (0x17a8 - 0x17a8)
#define AUD1_REGISTER_OFFSET                 (0x17ac - 0x17a8)
#define AUD2_REGISTER_OFFSET                 (0x17b0 - 0x17a8)
#define AUD3_REGISTER_OFFSET                 (0x17b4 - 0x17a8)
#define AUD4_REGISTER_OFFSET                 (0x17b8 - 0x17a8)
#define AUD5_REGISTER_OFFSET                 (0x17bc - 0x17a8)
#define AUD6_REGISTER_OFFSET                 (0x17c0 - 0x17a8)
#define AUD7_REGISTER_OFFSET                 (0x17c4 - 0x17a8)

/* hpd instance offsets */
#define HPD0_REGISTER_OFFSET                 (0x1898 - 0x1898)
#define HPD1_REGISTER_OFFSET                 (0x18a0 - 0x1898)
#define HPD2_REGISTER_OFFSET                 (0x18a8 - 0x1898)
#define HPD3_REGISTER_OFFSET                 (0x18b0 - 0x1898)
#define HPD4_REGISTER_OFFSET                 (0x18b8 - 0x1898)
#define HPD5_REGISTER_OFFSET                 (0x18c0 - 0x1898)

#define		PIPEID(x)					((x) << 0)
#define		MEID(x)						((x) << 2)
#define		VMID(x)						((x) << 4)
#define		QUEUEID(x)					((x) << 8)

#define MC_SEQ_MISC0__MT__MASK	0xf0000000
#define MC_SEQ_MISC0__MT__GDDR1  0x10000000
#define MC_SEQ_MISC0__MT__DDR2   0x20000000
#define MC_SEQ_MISC0__MT__GDDR3  0x30000000
#define MC_SEQ_MISC0__MT__GDDR4  0x40000000
#define MC_SEQ_MISC0__MT__GDDR5  0x50000000
#define MC_SEQ_MISC0__MT__HBM    0x60000000
#define MC_SEQ_MISC0__MT__DDR3   0xB0000000

/*
 * PM4
 */
#define	PACKET_TYPE0	0
#define	PACKET_TYPE1	1
#define	PACKET_TYPE2	2
#define	PACKET_TYPE3	3

#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF)
#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
#define PACKET0(reg, n)	((PACKET_TYPE0 << 30) |				\
			 ((reg) & 0xFFFF) |			\
			 ((n) & 0x3FFF) << 16)
#define CP_PACKET2			0x80000000
#define		PACKET2_PAD_SHIFT		0
#define		PACKET2_PAD_MASK		(0x3fffffff << 0)

#define PACKET2(v)	(CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))

#define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
			 (((op) & 0xFF) << 8) |				\
			 ((n) & 0x3FFF) << 16)

#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)

/* Packet 3 types */
#define	PACKET3_NOP					0x10

Annotation

Implementation Notes