drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
Extension
.asm
Size
55021 bytes
Lines
1435
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: drivers/gpu
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#define CHIP_NAVI10 26
#define CHIP_SIENNA_CICHLID 30
#define CHIP_PLUM_BONITO 36

#define NO_SQC_STORE (ASIC_FAMILY >= CHIP_SIENNA_CICHLID)
#define HAVE_XNACK (ASIC_FAMILY < CHIP_SIENNA_CICHLID)
#define HAVE_SENDMSG_RTN (ASIC_FAMILY >= CHIP_PLUM_BONITO)
#define HAVE_BUFFER_LDS_LOAD (ASIC_FAMILY < CHIP_PLUM_BONITO)
#define SW_SA_TRAP (ASIC_FAMILY == CHIP_PLUM_BONITO)
#define SAVE_AFTER_XNACK_ERROR (HAVE_XNACK && !NO_SQC_STORE) // workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger
#define SINGLE_STEP_MISSED_WORKAROUND 1	//workaround for lost MODE.DEBUG_EN exception when SAVECTX raised

#define S_COHERENCE glc:1
#define V_COHERENCE slc:1 glc:1
#define S_WAITCNT_0 s_waitcnt 0

var SQ_WAVE_STATUS_SPI_PRIO_MASK		= 0x00000006
var SQ_WAVE_STATUS_HALT_MASK			= 0x2000
var SQ_WAVE_STATUS_ECC_ERR_MASK			= 0x20000
var SQ_WAVE_STATUS_TRAP_EN_SHIFT		= 6
var SQ_WAVE_IB_STS2_WAVE64_SHIFT		= 11
var SQ_WAVE_IB_STS2_WAVE64_SIZE			= 1
var SQ_WAVE_LDS_ALLOC_GRANULARITY		= 8
var S_STATUS_HWREG				= HW_REG_STATUS
var S_STATUS_ALWAYS_CLEAR_MASK			= SQ_WAVE_STATUS_SPI_PRIO_MASK|SQ_WAVE_STATUS_ECC_ERR_MASK
var S_STATUS_HALT_MASK				= SQ_WAVE_STATUS_HALT_MASK
var S_SAVE_PC_HI_TRAP_ID_MASK			= 0x00FF0000
var S_SAVE_PC_HI_HT_MASK			= 0x01000000

var SQ_WAVE_STATUS_NO_VGPRS_SHIFT		= 24
var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT		= 12
var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE		= 9
var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE		= 8
var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT	= 24
var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE	= 4

#if ASIC_FAMILY < CHIP_PLUM_BONITO
var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT		= 8
#else
var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT		= 12
#endif

var SQ_WAVE_TRAPSTS_SAVECTX_MASK		= 0x400
var SQ_WAVE_TRAPSTS_EXCP_MASK			= 0x1FF
var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT		= 10
var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK		= 0x80
var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT		= 7
var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK		= 0x100
var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT		= 8
var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK		= 0x800
var SQ_WAVE_TRAPSTS_ILLEGAL_INST_SHIFT		= 11
var SQ_WAVE_TRAPSTS_EXCP_HI_MASK		= 0x7000
#if ASIC_FAMILY >= CHIP_PLUM_BONITO
var SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT		= 16
var SQ_WAVE_TRAPSTS_WAVE_START_MASK		= 0x20000
var SQ_WAVE_TRAPSTS_WAVE_START_SHIFT		= 17
var SQ_WAVE_TRAPSTS_WAVE_END_MASK		= 0x40000
var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK	= 0x100000
#endif
var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK		= 0x10000000

var SQ_WAVE_MODE_EXCP_EN_SHIFT			= 12
var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT	= 19

var SQ_WAVE_IB_STS_FIRST_REPLAY_SHIFT		= 15
var SQ_WAVE_IB_STS_REPLAY_W64H_SHIFT		= 25
var SQ_WAVE_IB_STS_REPLAY_W64H_MASK		= 0x02000000
var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK	= 0x003F8000

var SQ_WAVE_MODE_DEBUG_EN_MASK			= 0x800

Annotation

Implementation Notes