drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm
Extension
.asm
Size
63775 bytes
Lines
1557
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: drivers/gpu
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#define CHIP_GFX12 37
#define CHIP_GC_12_0_3 38

#define HAVE_XNACK (ASIC_FAMILY == CHIP_GC_12_0_3)
#define HAVE_57BIT_ADDRESS (ASIC_FAMILY == CHIP_GC_12_0_3)
#define HAVE_BANKED_VGPRS (ASIC_FAMILY == CHIP_GC_12_0_3)
#define NUM_NAMED_BARRIERS (ASIC_FAMILY == CHIP_GC_12_0_3 ? 0x10 : 0)
#define HAVE_CLUSTER_BARRIER (ASIC_FAMILY == CHIP_GC_12_0_3)
#define CLUSTER_BARRIER_SERIALIZE_WORKAROUND (ASIC_FAMILY == CHIP_GC_12_0_3)
#define RELAXED_SCHEDULING_IN_TRAP (ASIC_FAMILY == CHIP_GFX12)
#define HAVE_INSTRUCTION_FIXUP (ASIC_FAMILY == CHIP_GC_12_0_3)

#define SINGLE_STEP_MISSED_WORKAROUND 1	//workaround for lost TRAP_AFTER_INST exception when SAVECTX raised
#define HAVE_VALU_SGPR_HAZARD (ASIC_FAMILY == CHIP_GFX12)
#define WAVE32_ONLY (ASIC_FAMILY == CHIP_GC_12_0_3)
#define SAVE_TTMPS_IN_SGPR_BLOCK (ASIC_FAMILY >= CHIP_GC_12_0_3)

#if HAVE_XNACK && !WAVE32_ONLY
# error
#endif

#define ADDRESS_HI32_NUM_BITS ((HAVE_57BIT_ADDRESS ? 57 : 48) - 32)
#define ADDRESS_HI32_MASK ((1 << ADDRESS_HI32_NUM_BITS) - 1)

var SQ_WAVE_STATE_PRIV_ALL_BARRIER_COMPLETE_MASK	= 0x4 | (NUM_NAMED_BARRIERS ? 0x8 : 0) | (HAVE_CLUSTER_BARRIER ? 0x10000 : 0)
var SQ_WAVE_STATE_PRIV_SCC_SHIFT		= 9
var SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK		= 0xC00
var SQ_WAVE_STATE_PRIV_HALT_MASK		= 0x4000
var SQ_WAVE_STATE_PRIV_POISON_ERR_MASK		= 0x8000
var SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT		= 15
var SQ_WAVE_STATUS_WAVE64_SHIFT			= 29
var SQ_WAVE_STATUS_WAVE64_SIZE			= 1
var SQ_WAVE_STATUS_NO_VGPRS_SHIFT		= 24
var SQ_WAVE_STATUS_IN_WG_SHIFT			= 11
var SQ_WAVE_STATE_PRIV_ALWAYS_CLEAR_MASK	= SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK|SQ_WAVE_STATE_PRIV_POISON_ERR_MASK
var S_SAVE_PC_HI_TRAP_ID_MASK			= 0xF0000000

var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT		= 12
var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE		= 9
var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE		= 8
var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT		= 12

#if ASIC_FAMILY < CHIP_GC_12_0_3
var SQ_WAVE_LDS_ALLOC_GRANULARITY		= 9
#else
var SQ_WAVE_LDS_ALLOC_GRANULARITY		= 10
#endif

var SQ_WAVE_EXCP_FLAG_PRIV_ADDR_WATCH_MASK	= 0xF
var SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_SHIFT	= 4
var SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_MASK	= 0x10
var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT	= 5
var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK	= 0x20
var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_MASK	= 0x40
var SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT	= 6
var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK	= 0x80
var SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT	= 7
var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_MASK	= 0x100
var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT	= 8
var SQ_WAVE_EXCP_FLAG_PRIV_WAVE_END_MASK	= 0x200
var SQ_WAVE_EXCP_FLAG_PRIV_TRAP_AFTER_INST_MASK	= 0x800
var SQ_WAVE_TRAP_CTRL_ADDR_WATCH_MASK		= 0x80
var SQ_WAVE_TRAP_CTRL_TRAP_AFTER_INST_MASK	= 0x200

var SQ_WAVE_EXCP_FLAG_PRIV_NON_MASKABLE_EXCP_MASK= SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_MASK		|\
						  SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_MASK	|\
						  SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK		|\
						  SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_MASK	|\
						  SQ_WAVE_EXCP_FLAG_PRIV_WAVE_END_MASK		|\
						  SQ_WAVE_EXCP_FLAG_PRIV_TRAP_AFTER_INST_MASK

Annotation

Implementation Notes