drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
Extension
.asm
Size
47539 bytes
Lines
1136
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: drivers/gpu
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#define CHIP_VEGAM 18
#define CHIP_ARCTURUS 23
#define CHIP_ALDEBARAN 25
#define CHIP_GC_9_4_3 26
#define CHIP_GC_9_5_0 27

var ACK_SQC_STORE		    =	1		    //workaround for suspected SQC store bug causing incorrect stores under concurrency
var SAVE_AFTER_XNACK_ERROR	    =	1		    //workaround for TCP store failure after XNACK error when ALLOW_REPLAY=0, for debugger
var SINGLE_STEP_MISSED_WORKAROUND   =	(ASIC_FAMILY <= CHIP_ALDEBARAN)	//workaround for lost MODE.DEBUG_EN exception when SAVECTX raised

#if ASIC_FAMILY < CHIP_GC_9_4_3
#define VMEM_MODIFIERS slc:1 glc:1
#else
#define VMEM_MODIFIERS sc0:1 nt:1
#endif

/**************************************************************************/
/*			variables					  */
/**************************************************************************/
var SQ_WAVE_STATUS_SPI_PRIO_SHIFT  = 1
var SQ_WAVE_STATUS_SPI_PRIO_MASK   = 0x00000006
var SQ_WAVE_STATUS_HALT_MASK       = 0x2000
var SQ_WAVE_STATUS_PRE_SPI_PRIO_SHIFT   = 0
var SQ_WAVE_STATUS_PRE_SPI_PRIO_SIZE    = 1
var SQ_WAVE_STATUS_POST_SPI_PRIO_SHIFT  = 3
var SQ_WAVE_STATUS_POST_SPI_PRIO_SIZE   = 29
var SQ_WAVE_STATUS_ALLOW_REPLAY_MASK    = 0x400000
var SQ_WAVE_STATUS_ECC_ERR_MASK         = 0x20000

var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT	= 12
#if ASIC_FAMILY >= CHIP_GC_9_5_0
var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE	= 11
var LDS_RESTORE_GRANULARITY_BYTES	= 1280
#else
var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE	= 9
var LDS_RESTORE_GRANULARITY_BYTES	= 512
#endif
var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE	= 6
var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SIZE	= 3			//FIXME	 sq.blk still has 4 bits at this time while SQ programming guide has 3 bits
var SQ_WAVE_GPR_ALLOC_SGPR_SIZE_SHIFT	= 24

#if ASIC_FAMILY >= CHIP_ALDEBARAN
var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT	= 6
var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SHIFT	= 12
var SQ_WAVE_GPR_ALLOC_ACCV_OFFSET_SIZE	= 6
#else
var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT	= 8
#endif

var SQ_WAVE_TRAPSTS_SAVECTX_MASK    =	0x400
var SQ_WAVE_TRAPSTS_EXCP_MASK	    =	0x1FF
var SQ_WAVE_TRAPSTS_SAVECTX_SHIFT   =	10
var SQ_WAVE_TRAPSTS_ADDR_WATCH_MASK =	0x80
var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT =	7
var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK   =	0x100
var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT  =	8
var SQ_WAVE_TRAPSTS_HOST_TRAP_MASK  =	0x400000
var SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK =	0x800000
var SQ_WAVE_TRAPSTS_WAVE_END_MASK   =	0x1000000
var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK =  0x2000000
var SQ_WAVE_TRAPSTS_PRE_SAVECTX_MASK	=   0x3FF
var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SHIFT	=   0x0
var SQ_WAVE_TRAPSTS_PRE_SAVECTX_SIZE	=   10
var SQ_WAVE_TRAPSTS_POST_SAVECTX_MASK	=   0xFFFFF800
var SQ_WAVE_TRAPSTS_POST_SAVECTX_SHIFT	=   11
var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE	=   21
var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK	=   0x800
var SQ_WAVE_TRAPSTS_EXCP_HI_MASK	=   0x7000
var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK	=   0x10000000

Annotation

Implementation Notes