drivers/gpu/drm/amd/amdkfd/Kconfig

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdkfd/Kconfig

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdkfd/Kconfig
Extension
[no extension]
Size
1460 bytes
Lines
41
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: build/configuration rule
Status
atlas-only

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

# SPDX-License-Identifier: MIT
#
# Heterogeneous system architecture configuration
#

config HSA_AMD
	bool "HSA kernel driver for AMD GPU devices"
	depends on DRM_AMDGPU && (X86_64 || ARM64 || PPC64 || (RISCV && 64BIT) || (LOONGARCH && 64BIT))
	select HMM_MIRROR
	select MMU_NOTIFIER
	select DRM_AMDGPU_USERPTR
	help
	  Enable this if you want to use HSA features on AMD GPU devices.

config HSA_AMD_SVM
	bool "Enable HMM-based shared virtual memory manager"
	depends on HSA_AMD && DEVICE_PRIVATE
	default y
	select HMM_MIRROR
	select MMU_NOTIFIER
	help
	  Enable this to use unified memory and managed memory in HIP. This
	  memory manager supports two modes of operation. One based on
	  preemptions and one based on page faults. To enable page fault
	  based memory management on most GFXv9 GPUs, set the module
	  parameter amdgpu.noretry=0.

config HSA_AMD_P2P
	bool "HSA kernel driver support for peer-to-peer for AMD GPU devices"
	depends on HSA_AMD && PCI_P2PDMA
	help
	  Enable peer-to-peer (P2P) communication between AMD GPUs over
	  the PCIe bus. This can improve performance of multi-GPU compute
	  applications and libraries by enabling GPUs to access data directly
	  in peer GPUs' memory without intermediate copies in system memory.

	  This P2P feature is only enabled on compatible chipsets, and between
	  GPUs with large memory BARs that expose the entire VRAM in PCIe bus
	  address space within the physical address limits of the GPUs.

Annotation

Implementation Notes