drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h- Extension
.h- Size
- 7105 bytes
- Lines
- 205
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
kfd_priv.h
Detected Declarations
struct mqd_managerstruct mqd_user_context_save_area_header
Annotated Snippet
struct mqd_manager {
struct kfd_mem_obj* (*allocate_mqd)(struct mqd_manager *mm,
struct queue_properties *q);
void (*init_mqd)(struct mqd_manager *mm, void **mqd,
struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
struct queue_properties *q);
int (*load_mqd)(struct mqd_manager *mm, void *mqd,
uint32_t pipe_id, uint32_t queue_id,
struct queue_properties *p,
struct mm_struct *mms);
void (*update_mqd)(struct mqd_manager *mm, void *mqd,
struct queue_properties *q,
struct mqd_update_info *minfo);
int (*destroy_mqd)(struct mqd_manager *mm, void *mqd,
enum kfd_preempt_type type,
unsigned int timeout, uint32_t pipe_id,
uint32_t queue_id);
void (*free_mqd)(struct mqd_manager *mm, void *mqd,
struct kfd_mem_obj *mqd_mem_obj);
bool (*is_occupied)(struct mqd_manager *mm, void *mqd,
uint64_t queue_address, uint32_t pipe_id,
uint32_t queue_id);
int (*get_wave_state)(struct mqd_manager *mm, void *mqd,
struct queue_properties *q,
void __user *ctl_stack,
u32 *ctl_stack_used_size,
u32 *save_area_used_size);
int (*get_checkpoint_info)(struct mqd_manager *mm, void *mqd,
uint32_t *ctl_stack_size);
void (*checkpoint_mqd)(struct mqd_manager *mm,
void *mqd,
void *mqd_dst,
void *ctl_stack_dst);
void (*restore_mqd)(struct mqd_manager *mm, void **mqd,
struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
struct queue_properties *p,
const void *mqd_src,
const void *ctl_stack_src,
const u32 ctl_stack_size);
#if defined(CONFIG_DEBUG_FS)
int (*debugfs_show_mqd)(struct seq_file *m, void *data);
#endif
bool (*check_preemption_failed)(struct mqd_manager *mm, void *mqd);
uint64_t (*mqd_stride)(struct mqd_manager *mm,
struct queue_properties *p);
struct mutex mqd_mutex;
struct kfd_node *dev;
uint32_t mqd_size;
};
struct mqd_user_context_save_area_header {
/* Byte offset from start of user context
* save area to the last saved top (lowest
* address) of control stack data. Must be
* 4 byte aligned.
*/
uint32_t control_stack_offset;
/* Byte size of the last saved control stack
* data. Must be 4 byte aligned.
*/
uint32_t control_stack_size;
/* Byte offset from start of user context save
* area to the last saved base (lowest address)
* of wave state data. Must be 4 byte aligned.
*/
uint32_t wave_state_offset;
/* Byte size of the last saved wave state data.
* Must be 4 byte aligned.
*/
uint32_t wave_state_size;
};
struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm,
struct queue_properties *q);
Annotation
- Immediate include surface: `kfd_priv.h`.
- Detected declarations: `struct mqd_manager`, `struct mqd_user_context_save_area_header`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.