drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
Extension
.c
Size
22664 bytes
Lines
729
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (cu_per_sh[se][sh] > cu) {
					if (cu_mask[i / 32] & (1U << (i % 32))) {
						if (cu == 8 && sh == 0)
							se_mask[se] |= en_mask << 30;
						else
							se_mask[se] |= en_mask << (cu_inc + sh * 16);
					}
					i += inc;
					if (i >= cu_mask_count)
						return;
				}
			}
		}
		cu_inc += 2;
	}
}

static void update_cu_mask(struct mqd_manager *mm, void *mqd,
			   struct mqd_update_info *minfo, uint32_t inst)
{
	struct v12_1_compute_mqd *m;
	uint32_t se_mask[2] = {0};

	if (!minfo || !minfo->cu_mask.ptr)
		return;

	mqd_symmetrically_map_cu_mask_v12_1(mm,
		minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst);

	m = get_mqd(mqd);
	m->compute_static_thread_mgmt_se0 = se_mask[0];
	m->compute_static_thread_mgmt_se1 = se_mask[1];

	pr_debug("update cu mask to %#x %#x\n",
		m->compute_static_thread_mgmt_se0,
		m->compute_static_thread_mgmt_se1);
}

static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q)
{
	m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
}

static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm,
		struct queue_properties *q)
{
	u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);
	struct kfd_node *node = mm->dev;
	struct kfd_mem_obj *mqd_mem_obj;

	if (q->type == KFD_QUEUE_TYPE_COMPUTE)
		mqd_size *= NUM_XCC(node->xcc_mask);

	if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj))
		return NULL;

	return mqd_mem_obj;
}

static void init_mqd(struct mqd_manager *mm, void **mqd,
			struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
			struct queue_properties *q)
{
	uint64_t addr;
	struct v12_1_compute_mqd *m;
	u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size);

	m = (struct v12_1_compute_mqd *) mqd_mem_obj->cpu_ptr;
	addr = mqd_mem_obj->gpu_addr;

	memset(m, 0, mqd_size);

	m->header = 0xC0310800;
	m->compute_pipelinestat_enable = 1;
	m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
	m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
	m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
	m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
	m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF;
	m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF;
	m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF;
	m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF;
	m->compute_static_thread_mgmt_se8 = 0xFFFFFFFF;

	m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
			0x63 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;

	m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT;

	m->cp_mqd_base_addr_lo	= lower_32_bits(addr);

Annotation

Implementation Notes