drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_vi.h- Extension
.h- Size
- 12060 bytes
- Lines
- 507
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct pm4_mes_set_resourcesstruct pm4_mes_runliststruct pm4_mes_map_processstruct pm4_mes_map_queuesstruct pm4_mes_query_statusstruct pm4_mes_unmap_queuesstruct pm4_mec_release_memenum mes_set_resources_queue_type_enumenum mes_map_queues_queue_sel_vi_enumenum mes_map_queues_queue_type_vi_enumenum mes_map_queues_engine_sel_vi_enumenum mes_query_status_interrupt_sel_enumenum mes_query_status_command_enumenum mes_query_status_engine_sel_enumenum mes_unmap_queues_action_enumenum mes_unmap_queues_queue_sel_enumenum mes_unmap_queues_engine_sel_enumenum RELEASE_MEM_event_index_enumenum RELEASE_MEM_cache_policy_enumenum RELEASE_MEM_dst_sel_enumenum RELEASE_MEM_int_sel_enumenum RELEASE_MEM_data_sel_enum
Annotated Snippet
struct pm4_mes_set_resources {
union {
union PM4_MES_TYPE_3_HEADER header; /* header */
uint32_t ordinal1;
};
union {
struct {
uint32_t vmid_mask:16;
uint32_t unmap_latency:8;
uint32_t reserved1:5;
enum mes_set_resources_queue_type_enum queue_type:3;
} bitfields2;
uint32_t ordinal2;
};
uint32_t queue_mask_lo;
uint32_t queue_mask_hi;
uint32_t gws_mask_lo;
uint32_t gws_mask_hi;
union {
struct {
uint32_t oac_mask:16;
uint32_t reserved2:16;
} bitfields7;
uint32_t ordinal7;
};
union {
struct {
uint32_t gds_heap_base:6;
uint32_t reserved3:5;
uint32_t gds_heap_size:6;
uint32_t reserved4:15;
} bitfields8;
uint32_t ordinal8;
};
};
#endif
/*--------------------MES_RUN_LIST--------------------*/
#ifndef PM4_MES_RUN_LIST_DEFINED
#define PM4_MES_RUN_LIST_DEFINED
struct pm4_mes_runlist {
union {
union PM4_MES_TYPE_3_HEADER header; /* header */
uint32_t ordinal1;
};
union {
struct {
uint32_t reserved1:2;
uint32_t ib_base_lo:30;
} bitfields2;
uint32_t ordinal2;
};
union {
struct {
uint32_t ib_base_hi:16;
uint32_t reserved2:16;
} bitfields3;
uint32_t ordinal3;
};
union {
struct {
uint32_t ib_size:20;
uint32_t chain:1;
uint32_t offload_polling:1;
uint32_t reserved2:1;
uint32_t valid:1;
uint32_t process_cnt:4;
uint32_t reserved3:4;
} bitfields4;
uint32_t ordinal4;
};
};
#endif
/*--------------------MES_MAP_PROCESS--------------------*/
#ifndef PM4_MES_MAP_PROCESS_DEFINED
#define PM4_MES_MAP_PROCESS_DEFINED
Annotation
- Detected declarations: `struct pm4_mes_set_resources`, `struct pm4_mes_runlist`, `struct pm4_mes_map_process`, `struct pm4_mes_map_queues`, `struct pm4_mes_query_status`, `struct pm4_mes_unmap_queues`, `struct pm4_mec_release_mem`, `enum mes_set_resources_queue_type_enum`, `enum mes_map_queues_queue_sel_vi_enum`, `enum mes_map_queues_queue_type_vi_enum`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.