drivers/gpu/drm/amd/amdkfd/kfd_priv.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdkfd/kfd_priv.h- Extension
.h- Size
- 50665 bytes
- Lines
- 1644
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/hashtable.hlinux/mmu_notifier.hlinux/memremap.hlinux/mutex.hlinux/types.hlinux/atomic.hlinux/workqueue.hlinux/spinlock.huapi/linux/kfd_ioctl.hlinux/idr.hlinux/kfifo.hlinux/seq_file.hlinux/kref.hlinux/sysfs.hlinux/device_cgroup.hdrm/drm_file.hdrm/drm_drv.hdrm/drm_device.hdrm/drm_ioctl.hkgd_kfd_interface.hlinux/swap.hamd_shared.hamdgpu.h
Detected Declarations
struct kfd_nodestruct kfd_event_interrupt_classstruct kfd_device_infostruct kfd_mem_objstruct kfd_vmid_infostruct kfd_devstruct kfd_nodestruct kfd_devstruct queue_propertiesstruct mqd_update_infostruct queuestruct scheduling_resourcesstruct process_queue_managerstruct qcm_process_devicestruct kfd_process_devicestruct svm_range_liststruct kfd_processstruct amdkfd_ioctl_descstruct kfd_criu_process_priv_datastruct kfd_criu_device_priv_datastruct kfd_criu_bo_priv_datastruct kfd_criu_svm_range_priv_datastruct kfd_criu_queue_priv_datastruct kfd_criu_event_priv_datastruct process_queue_nodestruct packet_managerstruct packet_manager_funcsenum kfd_ioctl_flagsenum cache_policyenum kfd_mempoolenum kfd_unmap_queues_filterenum kfd_queue_typeenum kfd_queue_formatenum KFD_QUEUE_PRIORITYenum mqd_update_flagenum KFD_MQD_TYPEenum KFD_PIPE_PRIORITYenum kfd_pdd_boundenum kfd_criu_object_typeenum kfd_config_dequeue_wait_counts_cmdfunction kfd_process_gpuid_from_gpuidxfunction kfd_irq_is_from_nodefunction kfd_flush_tlbfunction kfd_flush_tlb_after_unmapfunction kfd_devcgroup_check_permissionfunction kfd_is_first_nodefunction kfd_debugfs_init
Annotated Snippet
struct kfd_event_interrupt_class {
bool (*interrupt_isr)(struct kfd_node *dev,
const uint32_t *ih_ring_entry, uint32_t *patched_ihre,
bool *patched_flag);
void (*interrupt_wq)(struct kfd_node *dev,
const uint32_t *ih_ring_entry);
};
struct kfd_device_info {
uint32_t gfx_target_version;
const struct kfd_event_interrupt_class *event_interrupt_class;
unsigned int max_pasid_bits;
unsigned int max_no_of_hqd;
unsigned int doorbell_size;
size_t ih_ring_entry_size;
uint8_t num_of_watch_points;
uint16_t mqd_size_aligned;
bool supports_cwsr;
bool needs_pci_atomics;
uint32_t no_atomic_fw_version;
unsigned int num_sdma_queues_per_engine;
unsigned int num_reserved_sdma_queues_per_engine;
};
unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev);
unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *kdev);
struct kfd_mem_obj {
uint32_t range_start;
uint32_t range_end;
uint64_t gpu_addr;
uint32_t *cpu_ptr;
void *mem;
};
struct kfd_vmid_info {
uint32_t first_vmid_kfd;
uint32_t last_vmid_kfd;
uint32_t vmid_num_kfd;
};
#define MAX_KFD_NODES 8
struct kfd_dev;
struct kfd_node {
unsigned int node_id;
struct amdgpu_device *adev; /* Duplicated here along with keeping
* a copy in kfd_dev to save a hop
*/
const struct kfd2kgd_calls *kfd2kgd; /* Duplicated here along with
* keeping a copy in kfd_dev to
* save a hop
*/
struct kfd_vmid_info vm_info;
unsigned int id; /* topology stub index */
uint32_t xcc_mask; /* Instance mask of XCCs present */
struct amdgpu_xcp *xcp;
/* Interrupts */
struct kfifo ih_fifo;
struct work_struct interrupt_work;
spinlock_t interrupt_lock;
/*
* Interrupts of interest to KFD are copied
* from the HW ring into a SW ring.
*/
bool interrupts_active;
uint32_t interrupt_bitmap; /* Only used for GFX 9.4.3 */
/* QCM Device instance */
struct device_queue_manager *dqm;
/* Global GWS resource shared between processes */
void *gws;
/* Clients watching SMI events */
struct list_head smi_clients;
spinlock_t smi_lock;
uint32_t reset_seq_num;
/* SRAM ECC flag */
atomic_t sram_ecc_flag;
/*spm process id */
unsigned int spm_pasid;
/* Maximum process number mapped to HW scheduler */
unsigned int max_proc_per_quantum;
Annotation
- Immediate include surface: `linux/hashtable.h`, `linux/mmu_notifier.h`, `linux/memremap.h`, `linux/mutex.h`, `linux/types.h`, `linux/atomic.h`, `linux/workqueue.h`, `linux/spinlock.h`.
- Detected declarations: `struct kfd_node`, `struct kfd_event_interrupt_class`, `struct kfd_device_info`, `struct kfd_mem_obj`, `struct kfd_vmid_info`, `struct kfd_dev`, `struct kfd_node`, `struct kfd_dev`, `struct queue_properties`, `struct mqd_update_info`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.