drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h
Extension
.h
Size
4788 bytes
Lines
162
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct phy_id_mapping {
	bool assigned;
	bool is_mst;
	uint8_t enc_hw_inst;
	u8 lct;
	u8 port_num;
	u8 rad[8];
};

struct crc_data {
	uint32_t crc_R;
	uint32_t crc_G;
	uint32_t crc_B;
	uint32_t frame_count;
	bool crc_ready;
};

struct crc_info {
	struct crc_data crc[MAX_CRC_WINDOW_NUM];
	spinlock_t lock;
};

struct crc_window_param {
	uint16_t x_start;
	uint16_t y_start;
	uint16_t x_end;
	uint16_t y_end;
	/* CRC window is activated or not*/
	bool enable;
	/* Update crc window during vertical blank or not */
	bool update_win;
	/* skip reading/writing for few frames */
	int skip_frame_cnt;
};

struct secure_display_crtc_context {
	/* work to notify PSP TA*/
	struct work_struct notify_ta_work;

	/* work to forward ROI to dmcu/dmub */
	struct work_struct forward_roi_work;

	struct drm_crtc *crtc;

	/* Region of Interest (ROI) */
	struct crc_window roi[MAX_CRC_WINDOW_NUM];

	struct crc_info crc_info;
};

struct secure_display_context {

	struct secure_display_crtc_context *crtc_ctx;
    /* Whether dmub support multiple ROI setting */
	bool support_mul_roi;
	enum secure_display_mode op_mode;
	bool phy_mapping_updated;
	int phy_id_mapping_cnt;
	struct phy_id_mapping phy_id_mapping[MAX_CRTC];
};
#endif

static inline bool amdgpu_dm_is_valid_crc_source(enum amdgpu_dm_pipe_crc_source source)
{
	return (source > AMDGPU_DM_PIPE_CRC_SOURCE_NONE) &&
	       (source < AMDGPU_DM_PIPE_CRC_SOURCE_MAX);
}

/* amdgpu_dm_crc.c */
#ifdef CONFIG_DEBUG_FS
int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
					struct dm_crtc_state *dm_crtc_state,
					enum amdgpu_dm_pipe_crc_source source);
int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name);
int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc,
				     const char *src_name,
				     size_t *values_cnt);
const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
						  size_t *count);
void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
#else
#define amdgpu_dm_crtc_set_crc_source NULL
#define amdgpu_dm_crtc_verify_crc_source NULL
#define amdgpu_dm_crtc_get_crc_sources NULL
#define amdgpu_dm_crtc_handle_crc_irq(x)
#endif

#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc);
void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc);

Annotation

Implementation Notes