drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c- Extension
.c- Size
- 50404 bytes
- Lines
- 1795
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
acpi/video.hlinux/string.hlinux/acpi.hlinux/i2c.hdrm/drm_atomic.hdrm/drm_probe_helper.hdrm/amdgpu_drm.hdrm/drm_edid.hdrm/drm_fixed.hdm_services.hamdgpu.hdc.hamdgpu_dm.hamdgpu_dm_irq.hamdgpu_dm_mst_types.hdpcd_defs.hdc/inc/core_types.hdm_helpers.hddc_service_types.hclk_mgr.h
Detected Declarations
enum mccs_op_codeenum mccs_op_buff_sizeenum vcp_reply_maskfunction edid_extract_panel_idfunction apply_edid_quirksfunction dm_helpers_parse_edid_capsfunction fill_dc_mst_payload_table_from_drmfunction dm_helpers_dp_update_branch_infofunction fieldsfunction dm_helpers_dp_mst_write_payload_allocation_tablefunction dm_helpers_dp_mst_poll_pending_down_replyfunction dm_helpers_dp_mst_send_payload_allocationfunction dm_helpers_dp_mst_update_mst_mgr_for_deallocationfunction dm_dtn_log_beginfunction dm_dtn_log_append_vfunction dm_dtn_log_endfunction dm_helpers_dp_mst_start_top_mgrfunction dm_helpers_dp_mst_stop_top_mgrfunction dm_helpers_dp_read_dpcdfunction dm_helpers_dp_write_dpcdfunction dm_helpers_submit_i2cfunction dm_helpers_execute_fused_iofunction execute_synaptics_rc_commandfunction apply_synaptics_fifo_reset_wafunction write_dsc_enable_synaptics_non_virtual_dpcd_mstfunction dm_helpers_dp_write_dsc_enablefunction dm_helpers_dp_write_hblank_reductionfunction dm_helpers_is_dp_sink_presentfunction dm_helpers_probe_acpi_edidfunction dm_helpers_read_acpi_edidfunction dm_helpers_read_vbios_hardcoded_edidfunction get_max_frl_ratefunction get_dsc_max_slicesfunction populate_hdmi_info_from_connectorfunction dm_helpers_read_local_edidfunction dm_helper_dmub_aux_transfer_syncfunction dm_helpers_dmub_set_config_syncfunction dm_set_dcn_clocksfunction dm_helpers_smu_timeoutfunction dm_helpers_init_panel_settingsfunction dm_helpers_override_panel_settingsfunction dm_helpers_free_gpu_memfunction dm_helpers_dmub_outbox_interrupt_controlfunction dm_helpers_mst_enable_stream_featuresfunction dm_helpers_dp_handle_test_pattern_requestfunction dm_set_phyd32clkfunction dm_helpers_dp_mst_update_branch_bandwidthfunction dm_get_adaptive_sync_support_type
Annotated Snippet
if (dc_alloc->vcp_id == target_payload->vcpi) {
dc_alloc->vcp_id = 0;
dc_alloc->slot_count = 0;
break;
}
}
ASSERT(i != copy_of_link_table.stream_count);
}
/* Fill payload info*/
for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
dc_alloc =
©_of_link_table.stream_allocations[i];
if (dc_alloc->vcp_id > 0 && dc_alloc->slot_count > 0) {
sa = &new_table.stream_allocations[new_table.stream_count];
sa->slot_count = dc_alloc->slot_count;
sa->vcp_id = dc_alloc->vcp_id;
new_table.stream_count++;
}
}
/* Overwrite the old table */
*table = new_table;
}
void dm_helpers_dp_update_branch_info(
struct dc_context *ctx,
const struct dc_link *link)
{}
static void dm_helpers_construct_old_payload(
struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_topology_state *mst_state,
struct drm_dp_mst_atomic_payload *new_payload,
struct drm_dp_mst_atomic_payload *old_payload)
{
struct drm_dp_mst_atomic_payload *pos;
int pbn_per_slot = dfixed_trunc(mst_state->pbn_div);
u8 next_payload_vc_start = mgr->next_start_slot;
u8 payload_vc_start = new_payload->vc_start_slot;
u8 allocated_time_slots;
*old_payload = *new_payload;
/* Set correct time_slots/PBN of old payload.
* other fields (delete & dsc_enabled) in
* struct drm_dp_mst_atomic_payload are don't care fields
* while calling drm_dp_remove_payload_part2()
*/
list_for_each_entry(pos, &mst_state->payloads, next) {
if (pos != new_payload &&
pos->vc_start_slot > payload_vc_start &&
pos->vc_start_slot < next_payload_vc_start)
next_payload_vc_start = pos->vc_start_slot;
}
allocated_time_slots = next_payload_vc_start - payload_vc_start;
old_payload->time_slots = allocated_time_slots;
old_payload->pbn = allocated_time_slots * pbn_per_slot;
}
/*
* Writes payload allocation table in immediate downstream device.
*/
bool dm_helpers_dp_mst_write_payload_allocation_table(
struct dc_context *ctx,
const struct dc_stream_state *stream,
struct dc_dp_mst_stream_allocation_table *proposed_table,
bool enable)
{
struct amdgpu_dm_connector *aconnector;
struct drm_dp_mst_topology_state *mst_state;
struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload;
struct drm_dp_mst_topology_mgr *mst_mgr;
aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
/* Accessing the connector state is required for vcpi_slots allocation
* and directly relies on behaviour in commit check
* that blocks before commit guaranteeing that the state
* is not gonna be swapped while still in use in commit tail
*/
if (!aconnector || !aconnector->mst_root)
return false;
mst_mgr = &aconnector->mst_root->mst_mgr;
mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state);
new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port);
Annotation
- Immediate include surface: `acpi/video.h`, `linux/string.h`, `linux/acpi.h`, `linux/i2c.h`, `drm/drm_atomic.h`, `drm/drm_probe_helper.h`, `drm/amdgpu_drm.h`, `drm/drm_edid.h`.
- Detected declarations: `enum mccs_op_code`, `enum mccs_op_buff_size`, `enum vcp_reply_mask`, `function edid_extract_panel_id`, `function apply_edid_quirks`, `function dm_helpers_parse_edid_caps`, `function fill_dc_mst_payload_table_from_drm`, `function dm_helpers_dp_update_branch_info`, `function fields`, `function dm_helpers_dp_mst_write_payload_allocation_table`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.