drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.h
Extension
.h
Size
5460 bytes
Lines
170
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct amdgpu_dm_ism_config {

	/**
	 * @filter_num_frames: Idle periods shorter than this number of frames
	 * will be considered a "short idle period" for filtering.
	 *
	 * 0 indicates no filtering (i.e. no idle allow delay will be applied)
	 */
	unsigned int filter_num_frames;

	/**
	 * @filter_history_size: Number of recent idle periods to consider when
	 * counting the number of short idle periods.
	 */
	unsigned int filter_history_size;

	/**
	 * @filter_entry_count: When the number of short idle periods within
	 * recent &filter_history_size reaches this count, the idle allow delay
	 * will be applied.
	 *
	 * 0 indicates no filtering (i.e. no idle allow delay will be applied)
	 */
	unsigned int filter_entry_count;

	/**
	 * @activation_num_delay_frames: Defines the number of frames to wait
	 * for the idle allow delay.
	 *
	 * 0 indicates no filtering (i.e. no idle allow delay will be applied)
	 */
	unsigned int activation_num_delay_frames;

	/**
	 * @filter_old_history_threshold: A time-based restriction on top of
	 * &filter_history_size. Idle periods older than this threshold (in
	 * number of frames) will be ignored when counting the number of short
	 * idle periods.
	 *
	 * 0 indicates no time-based restriction, i.e. history is limited only
	 * by &filter_history_size.
	 */
	unsigned int filter_old_history_threshold;

	/**
	 * @sso_num_frames: Number of frames to delay before enabling static
	 * screen optimizations, such as PSR1 and Replay low HZ idle mode.
	 *
	 * 0 indicates immediate SSO enable upon allowing idle.
	 */
	unsigned int sso_num_frames;
};

struct amdgpu_dm_ism_record {
	/**
	 * @timestamp_ns: When idle was allowed
	 */
	unsigned long long timestamp_ns;

	/**
	 * @duration_ns: How long idle was allowed
	 */
	unsigned long long duration_ns;
};

struct amdgpu_dm_ism {
	struct amdgpu_dm_ism_config config;
	unsigned long long last_idle_timestamp_ns;

	enum amdgpu_dm_ism_state current_state;
	enum amdgpu_dm_ism_state previous_state;

	struct amdgpu_dm_ism_record records[AMDGPU_DM_IDLE_HIST_LEN];
	int next_record_idx;

	struct delayed_work delayed_work;
	struct delayed_work sso_delayed_work;
};

#define ism_to_amdgpu_crtc(ism_ptr) \
	container_of(ism_ptr, struct amdgpu_crtc, ism)

void amdgpu_dm_ism_init(struct amdgpu_dm_ism *ism,
			struct amdgpu_dm_ism_config *config);
void amdgpu_dm_ism_fini(struct amdgpu_dm_ism *ism);
void amdgpu_dm_ism_commit_event(struct amdgpu_dm_ism *ism,
				enum amdgpu_dm_ism_event event);
void amdgpu_dm_ism_disable(struct amdgpu_display_manager *dm);
void amdgpu_dm_ism_force_full_power(struct amdgpu_display_manager *dm);
void amdgpu_dm_ism_enable(struct amdgpu_display_manager *dm);

Annotation

Implementation Notes