drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/bios/dce80/command_table_helper_dce80.c- Extension
.c- Size
- 6763 bytes
- Lines
- 251
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dm_services.hatom.hinclude/grph_object_id.hinclude/grph_object_defs.hinclude/bios_parser_types.h../command_table_helper.h
Detected Declarations
function filesfunction clock_source_id_to_atomfunction signal_type_to_atom_dig_modefunction hpd_sel_to_atomfunction dig_encoder_sel_to_atomfunction disp_power_gating_action_to_atom
Annotated Snippet
switch (id) {
case CLOCK_SOURCE_ID_PLL0:
*atom_pll_id = ATOM_PPLL0;
break;
case CLOCK_SOURCE_ID_PLL1:
*atom_pll_id = ATOM_PPLL1;
break;
case CLOCK_SOURCE_ID_PLL2:
*atom_pll_id = ATOM_PPLL2;
break;
case CLOCK_SOURCE_ID_EXTERNAL:
*atom_pll_id = ATOM_PPLL_INVALID;
break;
case CLOCK_SOURCE_ID_DFS:
*atom_pll_id = ATOM_EXT_PLL1;
break;
case CLOCK_SOURCE_ID_VCE:
/* for VCE encoding,
* we need to pass in ATOM_PPLL_INVALID
*/
*atom_pll_id = ATOM_PPLL_INVALID;
break;
case CLOCK_SOURCE_ID_DP_DTO:
/* When programming DP DTO PLL ID should be invalid */
*atom_pll_id = ATOM_PPLL_INVALID;
break;
case CLOCK_SOURCE_ID_UNDEFINED:
BREAK_TO_DEBUGGER(); /* check when this will happen! */
*atom_pll_id = ATOM_PPLL_INVALID;
result = false;
break;
default:
result = false;
break;
}
return result;
}
static uint8_t signal_type_to_atom_dig_mode(enum signal_type s)
{
uint8_t atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
switch (s) {
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_EDP:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP;
break;
case SIGNAL_TYPE_LVDS:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_LVDS;
break;
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
break;
case SIGNAL_TYPE_HDMI_TYPE_A:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_HDMI;
break;
case SIGNAL_TYPE_DISPLAY_PORT_MST:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DP_MST;
break;
default:
atom_dig_mode = ATOM_TRANSMITTER_DIGMODE_V5_DVI;
break;
}
return atom_dig_mode;
}
static uint8_t hpd_sel_to_atom(enum hpd_source_id id)
{
uint8_t atom_hpd_sel = 0;
switch (id) {
case HPD_SOURCEID1:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL;
break;
case HPD_SOURCEID2:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL;
break;
case HPD_SOURCEID3:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL;
break;
case HPD_SOURCEID4:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL;
break;
case HPD_SOURCEID5:
atom_hpd_sel = ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL;
break;
case HPD_SOURCEID6:
Annotation
- Immediate include surface: `dm_services.h`, `atom.h`, `include/grph_object_id.h`, `include/grph_object_defs.h`, `include/bios_parser_types.h`, `../command_table_helper.h`.
- Detected declarations: `function files`, `function clock_source_id_to_atom`, `function signal_type_to_atom_dig_mode`, `function hpd_sel_to_atom`, `function dig_encoder_sel_to_atom`, `function disp_power_gating_action_to_atom`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.