drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c

File Facts

System

Linux kernel

Corpus path

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30m_clk_mgr.c

Extension

.c

Size

1486 bytes

Lines

37

Domain

Driver Families

Bucket

drivers/gpu

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• clk_mgr_internal.h
• dcn30/dcn30m_clk_mgr.h
• dcn30m_clk_mgr_smu_msg.h

Detected Declarations

• function files

Annotated Snippet

#include "clk_mgr_internal.h"
#include "dcn30/dcn30m_clk_mgr.h"
#include "dcn30m_clk_mgr_smu_msg.h"


uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set)
{
	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	return dcn30m_smu_set_smart_mux_switch(clk_mgr, pins_to_set);
}

Annotation

• Immediate include surface: `clk_mgr_internal.h`, `dcn30/dcn30m_clk_mgr.h`, `dcn30m_clk_mgr_smu_msg.h`.
• Detected declarations: `function files`.
• Atlas domain: Driver Families / drivers/gpu.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.