drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/dcn301_smu.h
Extension
.h
Size
5171 bytes
Lines
165
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct vg_dpm_clocks {
	uint32_t DcfClocks[VG_NUM_DCFCLK_DPM_LEVELS];
	uint32_t DispClocks[VG_NUM_DISPCLK_DPM_LEVELS];
	uint32_t DppClocks[VG_NUM_DPPCLK_DPM_LEVELS];
	uint32_t SocClocks[VG_NUM_SOCCLK_DPM_LEVELS];
	uint32_t IspiClocks[VG_NUM_ISPICLK_DPM_LEVELS];
	uint32_t IspxClocks[VG_NUM_ISPXCLK_DPM_LEVELS];
	vcn_clk_t VcnClocks[VG_NUM_VCN_DPM_LEVELS];

	uint32_t SocVoltage[VG_NUM_SOC_VOLTAGE_LEVELS];

	df_pstate_t DfPstateTable[VG_NUM_FCLK_DPM_LEVELS];

	uint32_t MinGfxClk;
	uint32_t MaxGfxClk;

	uint8_t NumDfPstatesEnabled;
	uint8_t NumDcfclkLevelsEnabled;
	uint8_t NumDispClkLevelsEnabled;  //applies to both dispclk and dppclk
	uint8_t NumSocClkLevelsEnabled;

	uint8_t IspClkLevelsEnabled;  //applies to both ispiclk and ispxclk
	uint8_t VcnClkLevelsEnabled;  //applies to both vclk/dclk
	uint8_t spare[2];
};

struct smu_dpm_clks {
	struct vg_dpm_clocks *dpm_clks;
	union large_integer mc_address;
};

struct watermarks {
  // Watermarks
	WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];

	uint32_t     MmHubPadding[7]; // SMU internal use
};


struct display_idle_optimization {
	unsigned int df_request_disabled : 1;
	unsigned int phy_ref_clk_off     : 1;
	unsigned int s0i2_rdy            : 1;
	unsigned int reserved            : 29;
};

union display_idle_optimization_u {
	struct display_idle_optimization idle_info;
	uint32_t data;
};


int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
int dcn301_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
void dcn301_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
void dcn301_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);

#endif /* DAL_DC_301_SMU_H_ */

Annotation

Implementation Notes