drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
Extension
.c
Size
22558 bytes
Lines
692
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct IP_BASE_INSTANCE {
    unsigned int segment[MAX_SEGMENT];
};

struct IP_BASE {
    struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
};

#define regCLK1_CLK_PLL_REQ						0x0237
#define regCLK1_CLK_PLL_REQ_BASE_IDX			0

#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT		0x0
#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT	0xc
#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT	0x10
#define CLK1_CLK_PLL_REQ__FbMult_int_MASK		0x000001FFL
#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK		0x0000F000L
#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK		0xFFFF0000L

#define TO_CLK_MGR_DCN316(clk_mgr)\
	container_of(clk_mgr, struct clk_mgr_dcn316, base)

static int dcn316_get_active_display_cnt_wa(
		struct dc *dc,
		struct dc_state *context)
{
	int i, display_count;
	bool tmds_present = false;

	display_count = 0;
	for (i = 0; i < context->stream_count; i++) {
		const struct dc_stream_state *stream = context->streams[i];

		if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
				stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
				stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
			tmds_present = true;
		/* FRL can't be tracked by DIG enablement */
		if (dc_is_hdmi_frl_signal(stream->signal))
			display_count++;
	}

	for (i = 0; i < dc->link_count; i++) {
		const struct dc_link *link = dc->links[i];

		/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
		if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
				link->link_enc->funcs->is_dig_enabled(link->link_enc))
			display_count++;
	}

	/* WA for hang on HDMI after display off back back on*/
	if (display_count == 0 && tmds_present)
		display_count = 1;

	return display_count;
}

static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
		bool safe_to_lower, bool disable)
{
	struct dc *dc = clk_mgr_base->ctx->dc;
	uint8_t i;

	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
		struct pipe_ctx *pipe = safe_to_lower
			? &context->res_ctx.pipe_ctx[i]
			: &dc->current_state->res_ctx.pipe_ctx[i];

		if (pipe->top_pipe || pipe->prev_odm_pipe)
			continue;
		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||
				     !pipe->stream->link_enc)) {
			if (disable) {
				if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
					pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);

				reset_sync_context_for_pipe(dc, context, i);
			} else
				pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
		}
	}
}

static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base)
{
	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	dcn316_smu_enable_pme_wa(clk_mgr);
}

Annotation

Implementation Notes