drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c- Extension
.c- Size
- 58405 bytes
- Lines
- 1609
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dcn35_clk_mgr.hdccg.hclk_mgr_internal.hdce100/dce_clk_mgr.hdcn20/dcn20_clk_mgr.hreg_helper.hcore_types.hdcn35_smu.hdm_helpers.hdcn31/dcn31_clk_mgr.hdc_dmub_srv.hlink_service.hlogger_types.h
Detected Declarations
function dcn35_get_active_display_cnt_wafunction dcn35_disable_otg_wafunction dcn35_update_clocks_update_dtb_dtofunction dcn35_update_clocks_update_dpp_dtofunction get_lowest_dpia_indexfunction dcn35_notify_host_router_bwfunction dcn35_update_clocksfunction should_set_clockfunction get_vco_frequency_from_regfunction dcn35_enable_pme_wafunction dcn35_are_clock_states_equalfunction dcn35_save_clk_registers_internalfunction dcn35_save_clk_registersfunction dcn35_is_spll_ssc_enabledfunction init_clk_statesfunction dcn35_init_clocksfunction dcn35_read_ss_info_from_lutfunction dcn35_build_watermark_rangesfunction dcn35_notify_wm_rangesfunction dcn35_get_dpm_table_from_smufunction dcn351_get_dpm_table_from_smufunction find_max_clk_valuefunction is_valid_clock_valuefunction convert_wck_ratiofunction calc_dram_speed_mtsfunction dcn35_clk_mgr_helper_populate_bw_paramsfunction dcn35_set_low_power_statefunction dcn35_exit_low_power_statefunction dcn35_is_ips_supportedfunction dcn35_init_clocks_fpgafunction dcn35_update_clocks_fpgafunction dcn35_get_max_clock_khzfunction translate_to_DpmClocks_t_dcn35function dcn35_clk_mgr_constructfunction dcn35_clk_mgr_destroy
Annotated Snippet
if (!dc->config.unify_link_enc_assignment) {
if (new_pipe->stream)
new_pipe_link_enc = new_pipe->stream->link_enc;
if (pipe->stream)
pipe_link_enc = pipe->stream->link_enc;
}
stream_changed_otg_dig_on = old_pipe->stream && new_pipe->stream &&
old_pipe->stream != new_pipe->stream &&
old_pipe->stream_res.tg == new_pipe->stream_res.tg &&
new_pipe_link_enc && !new_pipe->stream->dpms_off &&
new_pipe_link_enc->funcs->is_dig_enabled &&
new_pipe_link_enc->funcs->is_dig_enabled(
new_pipe_link_enc) &&
new_pipe->stream_res.stream_enc &&
new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled &&
new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc);
if (old_pipe->stream && new_pipe->stream && old_pipe->stream == new_pipe->stream) {
has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&
dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);
has_active_hpo = has_active_hpo || (old_pipe->stream->signal == SIGNAL_TYPE_HDMI_FRL &&
new_pipe->stream->signal == SIGNAL_TYPE_HDMI_FRL);
}
if (!has_active_hpo && !stream_changed_otg_dig_on && pipe->stream &&
(pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || !pipe_link_enc) &&
!dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) {
/* This w/a should not trigger when we have a dig active */
if (disable) {
if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
reset_sync_context_for_pipe(dc, context, i);
} else {
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
}
}
}
}
static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
struct dc_state *context,
int ref_dtbclk_khz)
{
struct dccg *dccg = clk_mgr->dccg;
uint32_t tg_mask = 0;
uint32_t i;
for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
struct dtbclk_dto_params dto_params = {0};
/* use mask to program DTO once per tg */
if (pipe_ctx->stream_res.tg &&
!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ||
dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
if (pipe_ctx->stream_res.audio != NULL)
dto_params.req_audio_dtbclk_khz = 24000;
}
if (dc_is_hdmi_signal(pipe_ctx->stream->signal) ||
dc_is_dvi_signal(pipe_ctx->stream->signal))
dto_params.is_hdmi = true;
dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
//dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
}
}
}
static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
struct dc_state *context, bool safe_to_lower)
{
uint32_t i;
bool dppclk_active[MAX_PIPES] = {0};
clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
Annotation
- Immediate include surface: `dcn35_clk_mgr.h`, `dccg.h`, `clk_mgr_internal.h`, `dce100/dce_clk_mgr.h`, `dcn20/dcn20_clk_mgr.h`, `reg_helper.h`, `core_types.h`, `dcn35_smu.h`.
- Detected declarations: `function dcn35_get_active_display_cnt_wa`, `function dcn35_disable_otg_wa`, `function dcn35_update_clocks_update_dtb_dto`, `function dcn35_update_clocks_update_dpp_dto`, `function get_lowest_dpia_index`, `function dcn35_notify_host_router_bw`, `function dcn35_update_clocks`, `function should_set_clock`, `function get_vco_frequency_from_reg`, `function dcn35_enable_pme_wa`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.