drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c- Extension
.c- Size
- 15501 bytes
- Lines
- 509
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
core_types.hclk_mgr_internal.hreg_helper.hdm_helpers.hdcn35_smu.hmp/mp_14_0_0_offset.hmp/mp_14_0_0_sh_mask.hlogger_types.h
Detected Declarations
function filesfunction dcn35_smu_wait_for_responsefunction dcn35_smu_send_msg_with_paramfunction dcn35_smu_get_smu_versionfunction dcn35_smu_set_dispclkfunction dcn35_smu_set_dprefclkfunction dcn35_smu_set_hard_min_dcfclkfunction dcn35_smu_set_min_deep_sleep_dcfclkfunction dcn35_smu_set_dppclkfunction dcn35_smu_set_display_idle_optimizationfunction dcn35_smu_enable_phy_refclk_pwrdwnfunction dcn35_smu_enable_pme_wafunction dcn35_smu_set_dram_addr_highfunction dcn35_smu_set_dram_addr_lowfunction dcn35_smu_transfer_dpm_table_smu_2_dramfunction dcn35_smu_transfer_wm_table_dram_2_smufunction dcn35_smu_set_zstate_supportfunction dcn35_smu_get_dprefclkfunction dcn35_smu_get_dtbclkfunction dcn35_smu_set_dtbclkfunction dcn35_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwnfunction dcn35_smu_exit_low_power_statefunction dcn35_smu_get_ips_supportedfunction dcn35_smu_notify_host_router_bw
Annotated Snippet
#include "core_types.h"
#include "clk_mgr_internal.h"
#include "reg_helper.h"
#include "dm_helpers.h"
#include "dcn35_smu.h"
#include "mp/mp_14_0_0_offset.h"
#include "mp/mp_14_0_0_sh_mask.h"
/* TODO: Use the real headers when they're correct */
#define MP1_BASE__INST0_SEG0 0x00016000
#define MP1_BASE__INST0_SEG1 0x0243FC00
#define MP1_BASE__INST0_SEG2 0x00DC0000
#define MP1_BASE__INST0_SEG3 0x00E00000
#define MP1_BASE__INST0_SEG4 0x00E40000
#define MP1_BASE__INST0_SEG5 0
#ifdef BASE_INNER
#undef BASE_INNER
#endif
#define BASE_INNER(seg) MP1_BASE__INST0_SEG ## seg
#define BASE(seg) BASE_INNER(seg)
#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
#define FN(reg_name, field) \
FD(reg_name##__##field)
#include "logger_types.h"
#undef DC_LOGGER
#define DC_LOGGER \
CTX->logger
#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
#define VBIOSSMC_MSG_TestMessage 0x1
#define VBIOSSMC_MSG_GetSmuVersion 0x2
#define VBIOSSMC_MSG_PowerUpGfx 0x3
#define VBIOSSMC_MSG_SetDispclkFreq 0x4
#define VBIOSSMC_MSG_SetDprefclkFreq 0x5 //Not used. DPRef is constant
#define VBIOSSMC_MSG_SetDppclkFreq 0x6
#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x7
#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x8
#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x9 //Keep it in case VMIN dees not support phy clk
#define VBIOSSMC_MSG_GetFclkFrequency 0xA
#define VBIOSSMC_MSG_SetDisplayCount 0xB //Not used anymore
#define VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown 0xC //To ask PMFW turn off TMDP 48MHz refclk during display off to save power
#define VBIOSSMC_MSG_UpdatePmeRestore 0xD
#define VBIOSSMC_MSG_SetVbiosDramAddrHigh 0xE //Used for WM table txfr
#define VBIOSSMC_MSG_SetVbiosDramAddrLow 0xF
#define VBIOSSMC_MSG_TransferTableSmu2Dram 0x10
#define VBIOSSMC_MSG_TransferTableDram2Smu 0x11
#define VBIOSSMC_MSG_SetDisplayIdleOptimizations 0x12
#define VBIOSSMC_MSG_GetDprefclkFreq 0x13
#define VBIOSSMC_MSG_GetDtbclkFreq 0x14
#define VBIOSSMC_MSG_AllowZstatesEntry 0x15
#define VBIOSSMC_MSG_DisallowZstatesEntry 0x16
#define VBIOSSMC_MSG_SetDtbClk 0x17
#define VBIOSSMC_MSG_DispIPS2Entry 0x18 ///< Display IPS2 entry, DMU
#define VBIOSSMC_MSG_DispIPS2Exit 0x19 ///< Display IPS2 exit, DMU
#define VBIOSSMC_MSG_DisableLSdma 0x1A ///< Disable LSDMA; only sent by VBIOS
#define VBIOSSMC_MSG_DpControllerPhyStatus 0x1B ///< Inform PMFW about the pre conditions for turning SLDO2 on/off . bit[0]==1 precondition is met, bit[1-2] are for DPPHY number
#define VBIOSSMC_MSG_QueryIPS2Support 0x1C ///< Return 1: support; else not supported
#define VBIOSSMC_MSG_NotifyHostRouterBW 0x1D
#define VBIOSSMC_Message_Count 0x1E
#define VBIOSSMC_Status_BUSY 0x0
#define VBIOSSMC_Result_OK 0x1
#define VBIOSSMC_Result_Failed 0xFF
#define VBIOSSMC_Result_UnknownCmd 0xFE
#define VBIOSSMC_Result_CmdRejectedPrereq 0xFD
#define VBIOSSMC_Result_CmdRejectedBusy 0xFC
union dcn35_dpia_host_router_bw {
struct {
uint32_t hr_id : 16;
uint32_t bw_mbps : 16;
} bits;
uint32_t all;
};
/*
* Function to be used instead of REG_WAIT macro because the wait ends when
* the register is NOT EQUAL to zero, and because `the translation in msg_if.h
* won't work with REG_WAIT.
*/
static uint32_t dcn35_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
{
uint32_t res_val = VBIOSSMC_Status_BUSY;
Annotation
- Immediate include surface: `core_types.h`, `clk_mgr_internal.h`, `reg_helper.h`, `dm_helpers.h`, `dcn35_smu.h`, `mp/mp_14_0_0_offset.h`, `mp/mp_14_0_0_sh_mask.h`, `logger_types.h`.
- Detected declarations: `function files`, `function dcn35_smu_wait_for_response`, `function dcn35_smu_send_msg_with_param`, `function dcn35_smu_get_smu_version`, `function dcn35_smu_set_dispclk`, `function dcn35_smu_set_dprefclk`, `function dcn35_smu_set_hard_min_dcfclk`, `function dcn35_smu_set_min_deep_sleep_dcfclk`, `function dcn35_smu_set_dppclk`, `function dcn35_smu_set_display_idle_optimization`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.