drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h
Extension
.h
Size
3860 bytes
Lines
87
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dcn42_smu_watermark_set {
	struct dcn42_watermarks *wm_set;
	union large_integer mc_address;
};

struct dcn42_ss_info_table {
	uint32_t ss_divider;
	uint32_t ss_percentage[NUM_CLOCK_SOURCES];
};

struct clk_mgr_dcn42 {
	struct clk_mgr_internal base;
	struct dcn42_smu_watermark_set smu_wm_set;
};

bool dcn42_are_clock_states_equal(struct dc_clocks *a,
								  struct dc_clocks *b);
void dcn42_init_clocks(struct clk_mgr *clk_mgr);
void dcn42_update_clocks(struct clk_mgr *clk_mgr_base,
						 struct dc_state *context,
						 bool safe_to_lower);

void dcn42_clk_mgr_construct(struct dc_context *ctx,
							 struct clk_mgr_dcn42 *clk_mgr,
							 struct pp_smu_funcs *pp_smu,
							 struct dccg *dccg);

void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);

void dcn42_init_single_clock(unsigned int *entry_0,
			      uint32_t *smu_entry_0,
			      uint8_t num_levels);
unsigned int dcn42_convert_wck_ratio(uint8_t wck_ratio);
extern struct dcn42_ss_info_table dcn42_ss_info_table;
void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table);
void dcn42_enable_pme_wa(struct clk_mgr *clk_mgr_base);
void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base);
void dcn42_set_low_power_state(struct clk_mgr *clk_mgr_base);
void dcn42_exit_low_power_state(struct clk_mgr *clk_mgr_base);
unsigned int dcn42_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
bool dcn42_is_smu_present(struct clk_mgr *clk_mgr_base);
bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context);
int dcn42_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context, int *all_active_disps);
bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context);
void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower);
void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dtbclk_khz);
bool dcn42_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base);
struct dcn42_smu_dpm_clks; /* Forward declaration for pointer parameter below */
void dcn42_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, struct dcn42_smu_dpm_clks *smu_dpm_clks);
void dcn42_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int);
void dcn42_update_clocks_fpga(struct clk_mgr *clk_mgr, struct dc_state *context, bool safe_to_lower);
int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base);
#endif //__DCN42_CLK_MGR_H__

Annotation

Implementation Notes