drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
Extension
.c
Size
13153 bytes
Lines
431
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: MIT
//
// Copyright 2026 Advanced Micro Devices, Inc.



#include "core_types.h"
#include "clk_mgr_internal.h"
#include "reg_helper.h"
#include "dm_helpers.h"
#include "dcn42_smu.h"

#include "mp/mp_15_0_0_offset.h"
#include "mp/mp_15_0_0_sh_mask.h"

#ifdef BASE_INNER
#undef BASE_INNER
#endif

#define MP1_BASE__INST0_SEG0                       0x00016000
#define MP1_BASE__INST0_SEG1                       0x00016200
#define MP1_BASE__INST0_SEG2                       0x00E00000
#define MP1_BASE__INST0_SEG3                       0x00E80000
#define MP1_BASE__INST0_SEG4                       0x00EC0000
#define MP1_BASE__INST0_SEG5                       0x00F00000
#define MP1_BASE__INST0_SEG6                       0x02400400
#define MP1_BASE__INST0_SEG7                       0x0243F400
#define MP1_BASE__INST0_SEG8                       0x3C004000
#define MP1_BASE__INST0_SEG9                       0x3C3F4000

#define BASE_INNER(seg) MP1_BASE__INST0_SEG ## seg

#define BASE(seg) BASE_INNER(seg)

#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)

#define FN(reg_name, field) \
	FD(reg_name##__##field)

#include "logger_types.h"
#undef DC_LOGGER
#define DC_LOGGER \
	CTX->logger
#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }

// VBIOS and DAL to PMFW Interface

// DAL to PMFW interface registers
#define DAL_MSG_REG                             MP1_SMN_C2PMSG_71
#define DAL_RESP_REG                            MP1_SMN_C2PMSG_72
#define DAL_ARG_REG                             MP1_SMN_C2PMSG_73

/** @defgroup ResponseCodes PMFW Response Codes
*  @{
*/
// SMU Response Codes:
#define DALSMC_Result_OK                        0x01 ///< Message Response OK
#define DALSMC_Result_Failed                    0xFF ///< Message Response Failed
#define DALSMC_Result_UnknownCmd                0xFE ///< Message Response Unknown Command
#define DALSMC_Result_CmdRejectedPrereq         0xFD ///< Message Response Command Failed Prerequisite
#define DALSMC_Result_CmdRejectedBusy           0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message
/** @}*/

// Message Definitions:
/** @defgroup definitions Message definitions
*  @{
*/
#define DALSMC_MSG_TestMessage                  0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
#define DALSMC_MSG_GetPmfwVersion               0x02 ///< Get version
#define DALSMC_MSG_SetDispclkFreq               0x03 ///< Set display clock frequency in MHZ
#define DALSMC_MSG_SetDppclkFreq                0x04 ///< Set DPP clock frequency in MHZ
#define DALSMC_MSG_SetHardMinDcfclkByFreq       0x05 ///< Set DCF clock frequency hard min in MHZ
#define DALSMC_MSG_SetMinDeepSleepDcfclk        0x06 ///< Set DCF clock minimum frequency in deep sleep in MHZ
#define DALSMC_MSG_UpdatePmeRestore             0x07 ///< To ask PMFW to write into Azalia for PME wake up event
#define DALSMC_MSG_SetDramAddrHigh              0x08 ///< Set DRAM address high 32 bits for WM table transfer
#define DALSMC_MSG_SetDramAddrLow               0x09 ///< Set DRAM address low 32 bits for WM table transfer

#define DALSMC_MSG_TransferTableSmu2Dram        0x0A ///< Transfer table from PMFW SRAM to system DRAM
#define DALSMC_MSG_TransferTableDram2Smu        0x0B ///< Transfer table from system DRAM to PMFW
#define DALSMC_MSG_SetDisplayIdleOptimizations  0x0C ///< Set Idle state optimization for display off
#define DALSMC_MSG_GetDprefclkFreq              0x0D ///< Get DPREF clock frequency. Return in MHZ
#define DALSMC_MSG_GetDtbclkFreq                0x0E ///< Get DTB clock frequency. Return in MHZ
#define DALSMC_MSG_AllowZstatesEntry            0x0F ///< Inform PMFW of display allowing Zstate entry
#define DALSMC_MSG_SetDtbClk                    0x10 ///< Inform PMFW to turn of/off DTB cl0ck. arg = 1: turn DTB on with 600MHZ; arg = 0: turn DTB clk off
#define DALSMC_MSG_DispIPS2Exit                 0x11 ///< Display IPS2 exit

#define DALSMC_MSG_QueryIPS2Support             0x12 ///< Return 1: support; else not supported
#define DALSMC_Message_Count                    0x13 ///< Total number of VBIS and DAL messages
/** @}*/

Annotation

Implementation Notes