drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dc_ddc_types.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dc_ddc_types.h
Extension
.h
Size
5014 bytes
Lines
199
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct aux_request_transaction_data {
	enum aux_transaction_type type;
	enum i2caux_transaction_action action;
	/* 20-bit AUX channel transaction address */
	uint32_t address;
	/* delay, in 100-microsecond units */
	uint8_t delay;
	uint32_t length;
	uint8_t *data;
};

enum aux_transaction_reply {
	AUX_TRANSACTION_REPLY_AUX_ACK = 0x00,
	AUX_TRANSACTION_REPLY_AUX_NACK = 0x01,
	AUX_TRANSACTION_REPLY_AUX_DEFER = 0x02,
	AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK = 0x04,
	AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER = 0x08,

	AUX_TRANSACTION_REPLY_I2C_ACK = 0x00,
	AUX_TRANSACTION_REPLY_I2C_NACK = 0x10,
	AUX_TRANSACTION_REPLY_I2C_DEFER = 0x20,

	AUX_TRANSACTION_REPLY_HPD_DISCON = 0x40,

	AUX_TRANSACTION_REPLY_INVALID = 0xFF
};

struct aux_reply_transaction_data {
	enum aux_transaction_reply status;
	uint32_t length;
	uint8_t *data;
};

struct aux_payload {
	/* set following flag to read/write I2C data,
	 * reset it to read/write DPCD data */
	bool i2c_over_aux;
	/* set following flag to write data,
	 * reset it to read data */
	bool write;
	bool mot;
	bool write_status_update;

	uint32_t address;
	uint32_t length;
	uint8_t *data;
	/*
	 * used to return the reply type of the transaction
	 * ignored if NULL
	 */
	uint8_t *reply;
	/* expressed in milliseconds
	 * zero means "use default value"
	 */
	uint32_t defer_delay;

};
#define DEFAULT_AUX_MAX_DATA_SIZE 16

struct i2c_payload {
	bool write;
	uint8_t address;
	uint32_t length;
	uint8_t *data;
};

enum i2c_command_engine {
	I2C_COMMAND_ENGINE_DEFAULT,
	I2C_COMMAND_ENGINE_SW,
	I2C_COMMAND_ENGINE_HW
};

#define DDC_I2C_COMMAND_ENGINE I2C_COMMAND_ENGINE_SW

struct i2c_command {
	struct i2c_payload *payloads;
	uint8_t number_of_payloads;

	enum i2c_command_engine engine;

	/* expressed in KHz
	 * zero means "use default value" */
	uint32_t speed;
};

struct gpio_ddc_hw_info {
	bool hw_supported;
	uint32_t ddc_channel;
};

Annotation

Implementation Notes