drivers/gpu/drm/amd/display/dc/dc.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dc.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dc.h- Extension
.h- Size
- 140464 bytes
- Lines
- 3568
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dc_types.hdc_state.hdc_plane.hgrph_object_defs.hlogger_types.hhdcp_msg_types.hgpio_types.hlink_service_types.hgrph_object_ctrl_defs.hinc/hw/opp.hhwss/hw_sequencer.hinc/compressor.hinc/hw/dmcu.hdml/display_mode_lib.hdml2_0/dml2_wrapper.hdmub/inc/dmub_cmd.hdml/dml1_frl_cap_chk.hsspl/dc_spl_types.hdc_stream.hdc_dsc.h
Detected Declarations
struct abm_save_restorestruct aux_payloadstruct set_config_cmd_payloadstruct dmub_notificationstruct dcn_hubbub_reg_statestruct dcn_hubp_reg_statestruct dcn_dpp_reg_statestruct dcn_mpc_reg_statestruct dcn_opp_reg_statestruct dcn_dsc_reg_statestruct dcn_optc_reg_statestruct dcn_dccg_reg_statestruct frl_cap_chk_intermediates_fixed31_32struct frl_cap_chk_params_fixed31_32struct dc_versionsstruct dc_plane_capstruct rom_curve_capsstruct dpp_color_capsstruct lut3d_capsstruct mpc_color_capsstruct dc_color_capsstruct dc_dmub_capsstruct dc_scl_capsstruct dc_check_configstruct dc_capsstruct dc_bug_wastruct dc_dcc_surface_paramstruct dc_dcc_settingstruct dc_surface_dcc_capstruct dc_static_screen_paramsstruct surface_update_descriptorstruct dcstruct dc_plane_statestruct dc_statestruct dc_cap_funcsstruct link_training_settingsstruct dc_configstruct dc_clocksstruct dc_bw_validation_profilestruct pg_block_updatestruct dc_debug_datastruct dc_phy_addr_space_configstruct dc_virtual_addr_space_configstruct dc_bounding_box_overridesstruct dc_qos_infostruct dc_statestruct resource_poolstruct dce_hwseq
Annotated Snippet
struct frl_cap_chk_intermediates_fixed31_32 {
int c_frl_sb;
struct fixed31_32 overhead_sb;
struct fixed31_32 overhead_rs;
struct fixed31_32 overhead_map;
struct fixed31_32 overhead_min;
struct fixed31_32 overhead_max;
struct fixed31_32 f_pixel_clock_max;
struct fixed31_32 t_line;
struct fixed31_32 r_bit_min;
struct fixed31_32 r_frl_char_min;
struct fixed31_32 c_frl_line;
struct fixed31_32 ap;
struct fixed31_32 r_ap;
struct fixed31_32 avg_audio_packets_line;
struct fixed31_32 margin;
int audio_packets_line;
int blank_audio_min;
};
struct frl_cap_chk_params_fixed31_32 {
int lanes;
struct fixed31_32 f_pixel_clock_nominal; /* Pixel Clock rate (Hz) */
struct fixed31_32 r_bit_nominal; /* FRL bitrate (bps) */
int audio_packet_type;
struct fixed31_32 f_audio; /* Audio rate (Hz) */
int h_active; /* Active pixels per line */
int h_blank; /* Blanking pixels per line */
int bpc; /* Bits per component */
int vic; /* Video Identification Code */
enum hdmi_frl_pixel_encoding pixel_encoding;
bool compressed; /* set to true if DSC is enabled */
bool bypass_hc_target_calc; /* debug only */
bool allow_all_bpp; /* dsc_all_bpp */
/* DSC parameters */
int slices;
int slice_width;
struct fixed31_32 bpp_target;
int layout;
int acat; /* not supported */
/* outputs */
struct frl_dml_borrow_params borrow_params;
int average_tribyte_rate;
};
/* Display Core Interfaces */
struct dc_versions {
const char *dc_ver;
struct dmcu_version dmcu_version;
};
enum dp_protocol_version {
DP_VERSION_1_4 = 0,
DP_VERSION_2_1,
DP_VERSION_UNKNOWN,
};
enum dc_plane_type {
DC_PLANE_TYPE_INVALID,
DC_PLANE_TYPE_DCE_RGB,
DC_PLANE_TYPE_DCE_UNDERLAY,
DC_PLANE_TYPE_DCN_UNIVERSAL,
};
// Sizes defined as multiples of 64KB
enum det_size {
DET_SIZE_DEFAULT = 0,
DET_SIZE_192KB = 3,
DET_SIZE_256KB = 4,
DET_SIZE_320KB = 5,
DET_SIZE_384KB = 6
};
struct dc_plane_cap {
enum dc_plane_type type;
uint32_t per_pixel_alpha : 1;
struct {
uint32_t argb8888 : 1;
uint32_t nv12 : 1;
uint32_t fp16 : 1;
uint32_t p010 : 1;
uint32_t ayuv : 1;
} pixel_format_support;
// max upscaling factor x1000
// upscaling factors are always >= 1
Annotation
- Immediate include surface: `dc_types.h`, `dc_state.h`, `dc_plane.h`, `grph_object_defs.h`, `logger_types.h`, `hdcp_msg_types.h`, `gpio_types.h`, `link_service_types.h`.
- Detected declarations: `struct abm_save_restore`, `struct aux_payload`, `struct set_config_cmd_payload`, `struct dmub_notification`, `struct dcn_hubbub_reg_state`, `struct dcn_hubp_reg_state`, `struct dcn_dpp_reg_state`, `struct dcn_mpc_reg_state`, `struct dcn_opp_reg_state`, `struct dcn_dsc_reg_state`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.