drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
Extension
.h
Size
18621 bytes
Lines
553
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dccg_shift {
	DCCG_REG_FIELD_LIST(uint8_t)
	DCCG3_REG_FIELD_LIST(uint8_t)
	DCCG31_REG_FIELD_LIST(uint8_t)
	DCCG314_REG_FIELD_LIST(uint8_t)
	DCCG32_REG_FIELD_LIST(uint8_t)
	DCCG35_REG_FIELD_LIST(uint8_t)
	DCCG401_REG_FIELD_LIST(uint8_t)
	DCCG42_REG_FIELD_LIST(uint8_t)
};

struct dccg_mask {
	DCCG_REG_FIELD_LIST(uint32_t)
	DCCG3_REG_FIELD_LIST(uint32_t)
	DCCG31_REG_FIELD_LIST(uint32_t)
	DCCG314_REG_FIELD_LIST(uint32_t)
	DCCG32_REG_FIELD_LIST(uint32_t)
	DCCG35_REG_FIELD_LIST(uint32_t)
	DCCG401_REG_FIELD_LIST(uint32_t)
	DCCG42_REG_FIELD_LIST(uint32_t)
};

#define DCCG_REG_VARIABLE_LIST \
	uint32_t DPPCLK_DTO_CTRL; \
	uint32_t DPPCLK_DTO_PARAM[6]; \
	uint32_t REFCLK_CNTL; \
	uint32_t DISPCLK_FREQ_CHANGE_CNTL; \
	uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; \
	uint32_t HDMICHARCLK_CLOCK_CNTL[6]; \
	uint32_t PHYASYMCLK_CLOCK_CNTL; \
	uint32_t PHYBSYMCLK_CLOCK_CNTL; \
	uint32_t PHYCSYMCLK_CLOCK_CNTL; \
	uint32_t PHYDSYMCLK_CLOCK_CNTL; \
	uint32_t PHYESYMCLK_CLOCK_CNTL; \
	uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; \
	uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; \
	uint32_t DCCG_AUDIO_DTBCLK_DTO_MODULO; \
	uint32_t DCCG_AUDIO_DTBCLK_DTO_PHASE; \
	uint32_t DCCG_AUDIO_DTO_SOURCE; \
	uint32_t DPSTREAMCLK_CNTL; \
	uint32_t HDMISTREAMCLK_CNTL; \
	uint32_t SYMCLK32_SE_CNTL; \
	uint32_t SYMCLK32_LE_CNTL; \
	uint32_t DENTIST_DISPCLK_CNTL; \
	uint32_t DSCCLK_DTO_CTRL; \
	uint32_t DSCCLK0_DTO_PARAM; \
	uint32_t DSCCLK1_DTO_PARAM; \
	uint32_t DSCCLK2_DTO_PARAM; \
	uint32_t DSCCLK3_DTO_PARAM; \
	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE; \
	uint32_t DPSTREAMCLK_GATE_DISABLE; \
	uint32_t DCCG_GATE_DISABLE_CNTL; \
	uint32_t DCCG_GATE_DISABLE_CNTL2; \
	uint32_t DCCG_GATE_DISABLE_CNTL3; \
	uint32_t HDMISTREAMCLK0_DTO_PARAM; \
	uint32_t DCCG_GATE_DISABLE_CNTL4; \
	uint32_t OTG_PIXEL_RATE_DIV; \
	uint32_t DTBCLK_P_CNTL; \
	uint32_t DPPCLK_CTRL; \
	uint32_t DCCG_GATE_DISABLE_CNTL5; \
	uint32_t DCCG_GATE_DISABLE_CNTL6; \
	uint32_t DCCG_GLOBAL_FGCG_REP_CNTL; \
	uint32_t SYMCLKA_CLOCK_ENABLE; \
	uint32_t SYMCLKB_CLOCK_ENABLE; \
	uint32_t SYMCLKC_CLOCK_ENABLE; \
	uint32_t SYMCLKD_CLOCK_ENABLE; \
	uint32_t SYMCLKE_CLOCK_ENABLE; \
	uint32_t DP_DTO_MODULO[MAX_PIPES]; \
	uint32_t DP_DTO_PHASE[MAX_PIPES]; \
	uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; \
	uint32_t DCCG_AUDIO_DTO0_MODULE; \
	uint32_t DCCG_AUDIO_DTO0_PHASE; \
	uint32_t DCCG_AUDIO_DTO1_MODULE; \
	uint32_t DCCG_AUDIO_DTO1_PHASE; \
	uint32_t DCCG_CAC_STATUS; \
	uint32_t DCCG_CAC_STATUS2; \
	uint32_t DCCG_DISP_CNTL_REG; \
	uint32_t DCCG_DS_CNTL; \
	uint32_t DCCG_DS_DTO_INCR; \
	uint32_t DCCG_DS_DTO_MODULO; \
	uint32_t DCCG_DS_HW_CAL_INTERVAL; \
	uint32_t DCCG_GTC_CNTL; \
	uint32_t DCCG_GTC_CURRENT; \
	uint32_t DCCG_GTC_DTO_INCR; \
	uint32_t DCCG_GTC_DTO_MODULO; \
	uint32_t DCCG_PERFMON_CNTL; \
	uint32_t DCCG_PERFMON_CNTL2; \
	uint32_t DCCG_SOFT_RESET; \
	uint32_t DCCG_TEST_CLK_SEL; \
	uint32_t DCCG_VSYNC_CNT_CTRL; \

Annotation

Implementation Notes