drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
Extension
.c
Size
5163 bytes
Lines
167
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (req_dppclk) {
			/*
			 * program DPP DTO phase and modulo as below
			 * phase = ceiling(dpp_pipe_clk_mhz / 10)
			 * module = trunc(dpp_global_clk_mhz / 10)
			 *
			 * storing frequencies in registers allow dmcub fw
			 * to run time lower clocks when possible for power saving
			 *
			 * ceiling phase and truncate modulo guarentees the divided
			 * down per pipe dpp clock has high enough frequency
			 */
			phase = (req_dppclk + 9999) / 10000;

			if (phase > modulo) {
				/* phase > modulo result in screen corruption
				 * ie phase = 30, mod = 29 for 4k@60 HDMI
				 * in these case we don't want pipe clock to be divided
				 */
				phase = modulo;
			}
		} else {
			/*
			 *  set phase to 10 if dpp isn't used to
			 *  prevent hard hang if access dpp register
			 *  on unused pipe
			 *
			 *  DTO should be on to divide down un-used
			 *  pipe clock for power saving
			 */
			phase = 10;
		}

		REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
				DPPCLK0_DTO_PHASE, phase,
				DPPCLK0_DTO_MODULO, modulo);

		REG_UPDATE(DPPCLK_DTO_CTRL,
				DPPCLK_DTO_ENABLE[dpp_inst], 1);
	}

	dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
}

/*
 * On DCN21 S0i3 resume, BIOS programs MICROSECOND_TIME_BASE_DIV to
 * 0x00120464 as a marker that golden init has already been done.
 * dcn21_s0i3_golden_init_wa() reads this marker later in bios_golden_init()
 * to decide whether to skip golden init.
 *
 * dccg2_init() unconditionally overwrites MICROSECOND_TIME_BASE_DIV to
 * 0x00120264, destroying the marker before it can be read.
 *
 * Guard the call: if the S0i3 marker is present, skip init so the
 * WA can function correctly. bios_golden_init() will handle init in that case.
 *
 * DCN21 uses 48MHz refclk, not 100MHz, so we must explicitly set the correct
 * values (48MHz is taken from rn_clk_mgr_construct()).
 */
static void dccg21_init(struct dccg *dccg)
{
	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

	if (dccg2_is_s0i3_golden_init_wa_done(dccg))
		return;

	/* 48MHz refclk from rn_clk_mgr_construct() */
	REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120230);
	REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x0010bb80);
	REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c);

	if (REG(REFCLK_CNTL))
		REG_WRITE(REFCLK_CNTL, 0);
}

static const struct dccg_funcs dccg21_funcs = {
	.update_dpp_dto = dccg21_update_dpp_dto,
	.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
	.set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
	.otg_add_pixel = dccg2_otg_add_pixel,
	.otg_drop_pixel = dccg2_otg_drop_pixel,
	.dccg_init = dccg21_init,
	.refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
	.allow_clock_gating = dccg2_allow_clock_gating,
	.enable_memory_low_power = dccg2_enable_memory_low_power,
	.is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
};

struct dccg *dccg21_create(
	struct dc_context *ctx,

Annotation

Implementation Notes