drivers/gpu/drm/amd/display/dc/dccg/dcn302/dcn302_dccg.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dccg/dcn302/dcn302_dccg.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/display/dc/dccg/dcn302/dcn302_dccg.h- Extension
.h- Size
- 1590 bytes
- Lines
- 42
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
dcn30/dcn30_dccg.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __DCN302_DCCG_H__
#define __DCN302_DCCG_H__
#include "dcn30/dcn30_dccg.h"
#define DCCG_REG_LIST_DCN3_02() \
DCCG_COMMON_REG_LIST_DCN_BASE(),\
DCCG_SRII(DTO_PARAM, DPPCLK, 4)
#define DCCG_MASK_SH_LIST_DCN3_02(mask_sh) \
DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh)
#endif //__DCN302_DCCG_H__
Annotation
- Immediate include surface: `dcn30/dcn30_dccg.h`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.