drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
Extension
.c
Size
79627 bytes
Lines
2809
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (dccg35_is_fe_rcg(dccg, i) == 0) {
			if (dccg35_is_symclk_fe_src_functional_be(dccg, i, inst))
				dccg35_disable_symclk_fe_new(dccg, i);
		}
	}
	/* Safe to RCG SYMCLK*/
	dccg35_set_symclk_be_rcg(dccg, inst, true);
}

static void dccg35_enable_symclk32_se_new(
	struct dccg *dccg,
	int inst,
	enum symclk32_se_clk_source src)
{
	dccg35_set_symclk32_se_rcg(dccg, inst, false);
	dccg35_set_symclk32_se_src_new(dccg, inst, src);
}

static void dccg35_disable_symclk32_se_new(
	struct dccg *dccg,
	int inst)
{
	dccg35_set_symclk32_se_src_new(dccg, SYMCLK32_SE_REFCLK, inst);
	dccg35_set_symclk32_se_rcg(dccg, inst, true);
}

static void dccg35_enable_symclk32_le_new(
	struct dccg *dccg,
	int inst,
	enum symclk32_le_clk_source src)
{
	dccg35_set_symclk32_le_rcg(dccg, inst, false);
	dccg35_set_symclk32_le_src_new(dccg, inst, src);
}

static void dccg35_disable_symclk32_le_new(
	struct dccg *dccg,
	int inst)
{
	int i;

	/* Switch from functional clock to refclock */
	dccg35_set_symclk32_le_src_new(dccg, inst, SYMCLK32_LE_REFCLK);

	/* Check if any SE are connected and disable SE as well */
	for (i = 0; i < 4; i++) {
		/* Make sure FE is not already in RCG */
		if (dccg35_is_symclk32_se_rcg(dccg, i) == 0) {
			/* Disable and SE connected to this LE before RCG */
			if (dccg35_is_symclk32_se_src_functional_le_new(dccg, i, inst))
				dccg35_disable_symclk32_se_new(dccg, i);
		}
	}
	/* Safe to RCG SYM32_LE*/
	dccg35_set_symclk32_le_rcg(dccg, inst, true);
}

static void dccg35_enable_physymclk_new(struct dccg *dccg,
					int inst,
					enum physymclk_source src)
{
	dccg35_set_physymclk_rcg(dccg, inst, false);
	dccg35_set_physymclk_src_new(dccg, src, inst);
}

static void dccg35_disable_physymclk_new(struct dccg *dccg,
										 int inst)
{
	dccg35_set_physymclk_src_new(dccg, PHYSYMCLK_REFCLK, inst);
	dccg35_set_physymclk_rcg(dccg, inst, true);
}

static void dccg35_enable_dpp_clk_new(
	struct dccg *dccg,
	int inst,
	enum dppclk_clock_source src)
{
	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
	/* Sanitize inst before use in array de-ref */
	if (inst < 0) {
		BREAK_TO_DEBUGGER();
		return;
	}
	dccg35_set_dppclk_rcg(dccg, inst, false);
	dcn35_set_dppclk_src_new(dccg, inst, src);
	/* Switch DPP clock to DTO */
	REG_SET_2(DPPCLK_DTO_PARAM[inst], 0,
			  DPPCLK0_DTO_PHASE, 0xFF,
			  DPPCLK0_DTO_MODULO, 0xFF);
}

Annotation

Implementation Notes