drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
Extension
.c
Size
10173 bytes
Lines
370
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (force_enable) {
			REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
					PHYASYMCLK_ROOT_GATE_DISABLE, 1);
			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
					PHYASYMCLK_EN, 1,
					PHYASYMCLK_SRC_SEL, clk_src);
		} else {
			REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL,
					PHYASYMCLK_EN, 0,
					PHYASYMCLK_SRC_SEL, 0);
			REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
					PHYASYMCLK_ROOT_GATE_DISABLE,
					dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);
		}
		break;
	case 1:
		if (force_enable) {
			REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
					PHYBSYMCLK_ROOT_GATE_DISABLE, 1);
			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
					PHYBSYMCLK_EN, 1,
					PHYBSYMCLK_SRC_SEL, clk_src);
		} else {
			REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL,
					PHYBSYMCLK_EN, 0,
					PHYBSYMCLK_SRC_SEL, 0);
			REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
					PHYBSYMCLK_ROOT_GATE_DISABLE,
					dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);
		}
		break;
	case 2:
		if (force_enable) {
			REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
					PHYCSYMCLK_ROOT_GATE_DISABLE, 1);
			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
					PHYCSYMCLK_EN, 1,
					PHYCSYMCLK_SRC_SEL, clk_src);
		} else {
			REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL,
					PHYCSYMCLK_EN, 0,
					PHYCSYMCLK_SRC_SEL, 0);
			REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
					PHYCSYMCLK_ROOT_GATE_DISABLE,
					dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);
		}
		break;
	case 3:
		if (force_enable) {
			REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
					PHYDSYMCLK_ROOT_GATE_DISABLE, 1);
			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
					PHYDSYMCLK_EN, 1,
					PHYDSYMCLK_SRC_SEL, clk_src);
		} else {
			REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL,
					PHYDSYMCLK_EN, 0,
					PHYDSYMCLK_SRC_SEL, 0);
			REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
					PHYDSYMCLK_ROOT_GATE_DISABLE,
					dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);
		}
		break;
	case 4:
		if (force_enable) {
			REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
					PHYESYMCLK_ROOT_GATE_DISABLE, 1);
			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
					PHYESYMCLK_EN, 1,
					PHYESYMCLK_SRC_SEL, clk_src);
		} else {
			REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL,
					PHYESYMCLK_EN, 0,
					PHYESYMCLK_SRC_SEL, 0);
			REG_UPDATE(DCCG_GATE_DISABLE_CNTL2,
					PHYESYMCLK_ROOT_GATE_DISABLE,
					dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1);
		}
		break;
	default:
		BREAK_TO_DEBUGGER();
		return;
	}
}

static void dccg42_disable_hdmistreamclk(struct dccg *dccg)
{
	struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);

	REG_UPDATE_2(HDMISTREAMCLK_CNTL,

Annotation

Implementation Notes